CYW943907AEVAL1F external JTAG signals driving against FTDI JTAG signals

[kemyc_3518731]

On the CYW943907AEVAL1F evaluation board, I want to use an external JTAG device plugged into the J3 connector. I have looked at the example given in "OpenOCD-WICED", but I still have a question about the hardware connection. Aren't you driving against the JTAG signals coming from the FTDI chip if you close the SW4 switches and plug in a JTAG device?

[PriyaM_16]

Please follow this Downloading through Jlink Segger in WICED SDK 6.2 and future releases article to download through JLink.

When the SW4 is closed, the external JTAG gets connected to the FTDI_JTGA pins. Indeed the signals from FTDI chip FT2232 and the external JTAG signals are connected to same line when SW4 is closed.

[kemyc_3518731]

I reviewed the article you mentioned but, I'm still unclear as to how the FTDI signals don't interfere with the external JTAG signals. I assume there is no hardware changes required. Therefore, the FTDI chip must get configured into a mode where it does not drive these signals. Can you elaborate on the reason these signals don't conflict with each other?

[PriyaM_16 · Accepted solution]

Your understanding is correct. The configuration is such that we dont expect to program the chip using FTDI and external JTAG at the same time. When the device is powered up using 5V supply through the power jack J8 instead of USB, the external JTAG is used.

In case the device is powered using USB, WICED is forced to use the JLINK executable to download using JTAG. A flag need to be mentioned in the build string to ensure that JTAG is used.