USB superspeed peripherals Forum Discussions
Hello,
the FX3 TRM has chapter 10.9.4 UIB_POWER with register definition.
It specifies RESETN bit as only readable (R) by software. The description says:
```
After setting this bit to 1, firmware will poll and wait for the ‘active’ bit to assert. Reading ‘1’ from
‘resetn’ does not indicate the block is out of reset – this may take some time depending on initializa-
tion tasks and clock frequencies.
```
Is this bit writable from software (firmware) or is it read-only?
Additionally, 10.17.2 UIBIN_POWER has RESETN defined as R/W and description says:
```
This bit is nonfunctional for UIBIN and will not reset anything. Use UIB_POWER register instead.
```
Can you please clarify this discrepancy?
Thank you
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Hi Sir/Mam,
We wish to do configuration for FX3 board with our FPGA which is giving video stream at resolution 3264 * 2448 (active resolution) and 2560 * 1440 (active resolution).
I have previously implemented the design for 1920 * 1080 @ 60 fps by taking reference of application note AN75779, but now I want to check compatibility with higher resolutions as mentioned above. I have few questions regarding that -
1. Is FX3 board compatible to stream video data at 2k and 4k resolution?
2. What is the maximum frame rate at which I can stream video data?
3. what is the maximum resolution supported by the board?
4. How to calculate DMA buffer size for changed resolution and frame rate?
Please guide me for the above questions.
Thanks & Regards,
Akash
Show LessHello,
I see SX3 Utility FPGA Configuration has only 4 types of FPGA:
Lattice Crosslink
Xilinx Artix 7
Intel (Altera) Cyclone 10 LP
Lattice ECP5
Does it support another types of FPGA? Microchip PolarFire FPGA, for example: MPF300TL-FCSG536I
Thanks,
Michael
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Hello,
I'm trying to implement error handling for UVC controls on CX3. When a control is set to an invalid value, the device should respond with a STALL condition. This in turn causes the host driver to query the error code in a separate control transfer.
To do this, I need to read all of the OUT data of the control transfer, validate it, and decide whether to set the STALL condition. However the documentation for CyU3PUsbGetEP0Data has this:
If the control request is to be failed with a STALL handshake, the stall
call has to be made before all of the OUT data has been read. The request
will be completed with a positive ACK as soon as all of the OUT data has
been received by the device.
Is there any way around this limitation? I expected to have some way to keep EP0 in forced NAK until the firmware decides what to do, but nothing I have tried seemed to work.
Thanks!
Show LessHello,
Can the EZ-USB SX3 CYUSB3017 Device stream Video on USB 2.0 Lines and support commands transferring by Virtual COM simultaneously ?
The scenario is: Two Different PC Programs are opened:
- For Video Streaming through USB 2.0.
- For Commands Delivering. Virtual COM exists on USB 2.0. Video Streaming is happening & commands are sent simultaneously.
Can the EZ-USB SX3 CYUSB3017 Device stream Video on USB 3.0 Lines and support commands transferring by Virtual COM simultaneously ?
The scenario is: Two Different PC Programs are opened:
- For Video Streaming through USB 3.0.
- For Commands Delivering. Virtual COM exists on USB 3.0. Video Streaming is happening & commands are sent simultaneously.
Thanks a lot!
Show Lesscase CY_FX_RQT_UART_TX:
status = CyU3PUsbGetEP0Data(wLength, glEp0Buffer, &readCount);
if (status == CY_U3P_SUCCESS)
{
// CyU3PDebugPrint(4, glEp0Buffer);
CyU3PUartTransmitBytes (glEp0Buffer, readCount, &status);
if (status ! = CY_U3P_SUCCESS)
{
}
Regarding the function CyU3PDebugPrint, I can output it, but he can't output 0x00, a long string of data breaks at 0x00.
Besides, when I call CyU3PUartTransmitBytes function above, there is no output, is there something wrong?
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E8%B6%85%E9%AB%98%E9%80%9FUSB%E5%A4%96%E8%AE%BE/%E8%AF%B7%E6%95%99%E5%85%B3%E4%BA%8E-FX3-UART-%E5%8F%91%E9%80%81%E7%96%91%E6%83%91/td-p/719523
Show LessHello,
I have a few simple questions:
1) I have seen a few example schematics where an inductor is used (in conjunction with capacitors) to condition the voltage supply to AVDD, U3RXVDDQ, and U3TXVDDQ (a picture is attached). Different designers have used different inductor and capacitor values. What values for the inductor (inductance) and capacitor(s) are recommended?
2) Related to 1 above, is the resistance of the inductor of any importance? If so, please provide a min. and max. range; I can only find 10 ohm values in the package I need
Thanks,
Mo
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Hello
When designing the state machine in GPIF designer I can not access to the thread number as shown in the attachment,
How I can solve this issue?
Thanks.
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