USB superspeed peripherals Forum Discussions

I want to have my FPGA service 2 producer/consumer endpoints. One will use packet bursting and one a single USB 3.0 packet. I have the bursting EP working... beautiful... but I simply can't figure out how, with the FX3 API,  to add the second endpoint using a smaller buffer. In all, I want 1 thread assigned to each of the data transfer directions for each of the 2 endpoints. I've compiled an image file with what I'd hoped were the proper changes to the basic synchronous slave fifo firmware design example in thre SDK but the second  endpoint doesn't show up in the Control Center application. Anyone have suggestions? I'm finding the documentation and examples lacking as guidance and have no prior experience with the Cypress tools.

Hi,

I have connected FX3 Evaluation board to USB 3.0 host controller on my PC loaded with UVC example firmware. Here I want to know that whether it is working in Super speed or High speed. How to check this?

Thanks,

Subbarao.

 Hi,

Hi,

If you are compiling your older projects with the SDKv1.2 you might see some compilation and linker errors.

If you are seeing any, please do the following things:

change your cyfx_gcc_startup.S file according to the latest SDK

add this in the linker paths - "${FX3_INSTALL_PATH}\firmware\u3p_firmware\lib\fx3_debug\cyu3lpp.a".

If you see any other errors please post them here.

Thanks,

sai krishna.

Hey folks--

-

We've noticed some issues with the following setup: MacBook Pro Retina (host) + Parallels 7 + Win7 or Linux (guest).  We were wondering if anyone else had tried this configuration with the FX3.

-

The firmware we're testing works great on Win7 (native) and Linux (FC17, native) as well as the MacBook Pro Retina (native).  Parallels only recently provided support for USB 3.0 in guests (maybe a month or two ago).  In the above configuration, control transfers work just fine.

-

On Windows gues, PC to Device bulk transfers work just fine.  Endpoint 2.  However, Device-to-PC transfers "hang".  Our Beagle trace shows the frames through the last control transfer, then start "Periodic Timeout".

-

On Linux guest, both directions appear to hang with the same "Periodic Timeout".

-

We've started a support ticket with the folks at Parallels to investigate, but it will take a while before we reach a support tier with sufficient technical involvement to know if this is something on our end or their end or somewhere in between.  Just curious if anyone else here has replicated the issue.

Hello,

is it possible to send a zero length packet from a gpif callback?

i use a slavefifosync like design.

I configured the the P to U Channel to CY_U3P_DMA_TYPE_MANUAL

I do not use a U to P Channel.

I tried it like this:

void CyFxGpifCB (CyU3PGpifEventType event,uint8_t currentState)
{
   if (event == CYU3P_GPIF_EVT_SM_INTERRUPT)
   {
       if (currentState == ZLP)
          {
            CyU3PReturnStatus_t status = CY_U3P_SUCCESS;
            status = CyU3PDmaChannelCommitBuffer (&glChHandleSlFifoPtoU, 0, 0);    // send ZLP
            if (status != CY_U3P_SUCCESS)
              CyU3PDebugPrint (4, "CyU3PDmaChannelCommitBuffer GPIF CB failed, Error code = %x\n", status);
         }
    }
}

void CyFxSlFifoPtoUDmaCallback (CyU3PDmaChannel *chHandle,CyU3PDmaCbType_t  type,
                                CyU3PDmaCBInput_t *input)
{
    CyU3PReturnStatus_t status = CY_U3P_SUCCESS;
    if (type == CY_U3P_DMA_CB_PROD_EVENT)
    {
        if(input->buffer_p.count!=0)
        {
         status = CyU3PDmaChannelCommitBuffer (chHandle, input->buffer_p.count, 0);
        if (status != CY_U3P_SUCCESS)
           CyU3PDebugPrint (4, "CyU3PDmaChannelCommitBuffer DMA CB failed, Error code = %d\n", status);
       
        }
    }
}

but i get the error code "CyU3PDmaChannelCommitBuffer GPIF CB failed, Error code = 0x47"

Is there some other way ?

best regards

g.

Hi,

I am trying to use a onboard USB3.0 interface from intel chipset Z77 (Mainboard MSI Z77A-G45) with the FX3.

This USB3.0 xHCI Host always tries to set the device into low power mode U1. Why? If I reject that, then my application runs. But in the case it runs, the performance is worse. The link is connected through USB3 super speed but the reached speed without transfers is equal to a USB2.0 high speed connection.

Regards,

lumpi

Hello, I changed the crystal(19.2MHz) to oscillator. The voltage amplitude of the clock signal(clkin) on my board is 0.8V(19.2MHz)and the board is not working now. My question is that what should the voltage level of the clock be. 0.8V is too low or sufficient?

Thank you 

Lehua Chen  

hello:

i use fx3 to get image data from fpga,but the fpga set the pktend pin frequently per frame,i can't get a  complete frame by using cyapi.lib,can you tell me how can i use the api to get image frame completly.

 when i used the syn slave fifo example to transfer data from fpga to pc,my fpga give data at the speed of 20M/s(i use a FIFO in my fpga),i still want to let the FX3 works at the PCLK of 100MHz and 32bit mode ,so i think i have to use PKTEND to transfer short packets,then the problems come. i can't get the correct data, somebody can tell me about this problems? the handbook says that the PKTEND is used at the last word to be transfer, when i transfer a short packet , can i go on transfer a full packet or a short packet and go on and go on.....,

regards.

lint