USB superspeed peripherals Forum Discussions
I have a project that was build for the FX2LP in Keil uVision C51, and now I am trying to build, compile and use that same program on the FX3. I have followed all the online instructions for the MDK-ARM plugin, and need to know if there are more things I am missing. I'm sure there are, however if there are libraries, configuration settings, possibly using MinGW or PATH changes? Any help would be amazing.
Show LessI dont know if there is a way to reset the fx3 device without disconnecting from the usb host. Just doing a usb stack reset, is there any way to achive that?, I noticed in my application that works for the very first Gpif2 transaction but after that, and after reset the dma channel, endpoint, etc there is no way to take the app works again, sometimes its works 3 times, sometimes 8 times, but finally it crash. So again anybody know a safe way to restore the device and the usb stack to initial condition, thanks.
(I follow the lines includes in the troubleshotting guide about the way to reset dma channel keeping the endpoint in nak state.)
Show LessI would like to operate the slavefifo_examples program to 32bit.
#define CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT (1)
1. Set as shown above in the code, also compiled using the FX3 SDK
2. Run the compiled images from the test board.
3. Check the return data from a function CyU3PGpifLoad
apiRetStatus = CyU3PGpifLoad(&Sync_Slave_Fifo_2Bit_CyFxGpifConfig);
SDK ver 1.3.1 : CY_U3P_SUCCESS
SDK ver 1.3.3 : CY_U3P_ERROR_NOT_SUPPORTED /* if a 32 bit GPIF configuration is being used on a part that does not support this */
In order to use 32bit FX3 SDK v1.3.3, Is there a need to set up?
Will that make any difference to the library 1.3.1 and 1.3.3?
Library folder "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\u3p_firmware\lib" of files, "ver 1.3.1" if the file to be replaced, CY_U3P_SUCCESS the return will be.
cy_as0260.a
cy_ov5640.a
cyfxapi.a
cyu3lpp.a
cyu3mipicsi.a
cyu3sport.a
cyu3threadx.a
thank you.
Show LessHello,
I am reading data of a parallel 16 bit ADC through the FX3's GPIF. It seems to work fine as I observe different values in the Streamer for different input signals.
However I haven't figured out yet, how to obtain the ADC's 16 bit values from the hexadecimal data which is displayed in the Streamer.
For example: Without applying any signals to the GPIF I get something like this:
3FB0 EE FF FF 7D EE FF FF 7D EE FF FF 7D EE FF FF 7D
3FC0 EE FF FF 7D EE FF FF 7D EE FF FF 7D EE FF FF 7D
3FD0 EE FF FF 7D EE FF FF 7D EE FF FF 7D EE FF FF 7D
3FE0 EE FF FF 7D EE FF FF 7D EE FF FF 7D EE FF FF 7D
3FF0 EE FF FF 7D EE FF FF 7D EE FF FF 7D EE FF FF 7D
Is there any application note describing how to deal with the data ?
Thanks a lot
Show LessHi
I using UVC with image sensor.
Is it possible 16bit bus swap in 8bit-data mode (not using 16bit-data)?
ex) D0 ~ D7 <-> D8 ~ D15 , swap data.
Is it possible with gpif designer or firmware coding ?
Show LessIf I were trying to set up the FX3 to have a EEPROM on i2c, an FPGA and SPI flash chip both set up on SPI, how and what files would I need to include in my project to enable the set up of the DMA to manage this? Does the uC even need to interact with the interfaces, or can the DMA manage it on its own?
Show LessWhat is the thermal resistance between the junction and the case (Theta-JC) and the junction and the board (Theta-JB) for the FX3 121-ball BGA package?
Show LessI would like to have UART debugging enabled in my project. For that, I check UART box on the interface definition tab in the GPIF Designer (I modify the AN75779 project). Then, I save the project and build it. Everything is successful. Then, I close that project and open it again, but the UART box is unchecked. What could it be?
Show LessIn AN65974, there is a section title General Formulas for Using Partial Flags. The wording seems clear and the examples that follow confirm what I'm reading. However, in the example FPGA designs, the logic seems to be missing 1 clock cycle in how it deals with the partial flags. I ran some RTL simulation on the project files and read the description in the application note.
According to the formula, if the watermark value is 6 for a 32-bit bus, the number of clock cycles for a write = 2. It says:
"The number of data words that may be written after the clock edge at which the partial flag is sampled low"
If FlagB is asserted low (after the rising edge #0), it is 'sampled' on the rising edge #1. Then, SLWR# can be asserted for two more clocks after that, meaning rising edge #2, and #3. It is removed after rising edge #3. Correct? Why does the FPGA example do this one clock earlier (also, for the read case)?
CYoung
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