USB superspeed peripherals Forum Discussions

I have a sensor Aptina MT9V034 that is configured to run at 60 fps. I used a Cypress FX3 to control the sensor and communicate with an android application which uses UVCCam library.

I use the source code of AN75779 example which is compatible with UVC.

When using a software on pc to read the video from the camera it works fine without a problem.

However on my android application, after getting the frame of camera I do some image processing so my android application processes only around 30 fps (not fixed) and I get occasionally error code 71 which means CY_U3P_ERROR_INVALID_SEQUENCE after calling the function CyU3PDmaMultiChannelCommitBuffer. This error causes the frame sent by camera looks abnormally but until another error of invalid sequence occurs, the frame returns to normal.

As I understand the error is caused by the slow consumption of frame of my android application.

If that is the case which is the best solution to get rid of the error or to handle the error correctly so that I do not have to lower the frame rate of the sensor and the android application's slow consumption of frame doesn't affect the frame sent by the camera ?

Thank you very much.

Hi,

I am developing a USB camera in Cx3 with OV5640(MIPI Interface).

CX3 USB camera connection with a PC preview to normal operation,

It does not work when connected to Android phone with VGA resolution. (Using Android USB APP. ex, Webeecam)

How do I modify the UVC-related sources?

And, ask if I can get a solution or provide relevant reference source.

Thanks.

Hi,

I want your USB audio class example working for Linux platform (esp. Android phone) with the parameters below

a) 16kHZ Sampling Frequency

b) 16 bit per sample

c) Stereo mode

As per the last few questions posted, I have made the changes Cypress team asked to do me. Surprisingly, the audio streamed was  not correct. The recorded audio when played back had breaking, looking like duplicated audio samples which made the actual sound content elongated.

Please help to sort out this issue. If this issue is reproduced at your end or is it just me getting this problem? I am really confused.

Below are the changes you asked me to do in the original UAC source

1) sampling frequency in audio format descriptor :     0x80, 0x3E, 0x00, 

2) Transaction size in Endpoint descriptor for ISO streaming Audio data 0x20, 0x00,

3) Bytes per interval in  Super speed endpoint companion descriptor:   0x20, 0x00, 

4) in the cyfxuac.c file, change the macro definition to: CY_FX3_ISO_XFER_LEN                             (32)

NOTE:- SPI flash contains audio file flashed of same parameters aforementioned.

Dear Sir,

I want to use FX3 to transmit 4k * 2K image video to PC host, because of its huge throughput, I want to use all 32bit GPIF dada bus,e.g. pclk,frame sync(Vertical sync),line sync(Horizontal) and 32bit data bus.

But When I use GPIF II densign tool to configure this setting, I cannot configure databus to 32bit, it seems 16bit is the max limit.

Please see the attached screenshot.

Best,

David

I am supposed to create a GPIF II state machine on a master FX3 (CYUSB3014) USB Super Speed controller to load a slave device. A transition low to high on CTL0 would latch the data on 32-bit bus into the slave conditioned by a minimum 5ns setup time.

My approach: I use GPIF II Designer for FX3, I/F type is “Master”, Communication type is “Asynchronous”, 32-bit bus, one single control “CTL0”, CTL0 is “Early” and “Toggle”, initially 1 (high).

State machine states: START, IDLE, DATA_CTRL, REMOVE_DATA

In DATA_CTRL “Repeat Count is 1”, Repeat actions until next transition, DR_DATA, DR_GPIO (CTL0). This state (in my opinion and intentions) should last exactly 2 clocks and because CTL0 is “toggle” and initialized to “high”, the first clock CTL0 will be driven low and the second clock will be high, so I generate the low to high transition that will latch DATA on 32 bits into the slave.

In DR_DATA I have “Update new value from data source” checked, data source is “Socket”, Thread number is “Thread0”, and “Remove data from data source” is NOT checked.

In state REMOVE_DATA all user i/f is disabled with the exception of “Remove data from data source”. Of course, I have a DR_DATA action added in this state. My intention here is just to remove source data used in previous state. I expect here to have CTL0 stay untouched (left “HIGH” from the previous state) and after this action state machine should point to next unused data word.

I read all the possible documents but because things don’t work and I have not the optimal electronic means to check, I need advise and/or assurance from somebody more experienced and knowledgeable on the above.

Thank you in advance for your help.

PS. Another question: If in a DR_DATA of a state I have “Remove data from data source” NOT checked, can I combine it with a next state where I have “Update new value from data source” checked and “Remove data from data source” checked and can I be sure that in these 2 states one single data word is actually addressed until removal?

Working through the book "SuperSpeed Device - Design by Example", at the Ch.4 Example 7 there is mention of hooks from Cypress in regard with threads/semaphores/etc.. indicating when changes occurs, so that the Engineer can monitor with a Logic Analyzer on GPIO pins such sequences, in Real-Time.

There is a phrase in the book at pg.87: "At my request, Cypress have added an RTOS kernel hook that informs us when it starts up a new thread and when this thread suspends". Looking in the ProfileDebug's makefile of the Example 7, there is a line there that calls the gcc compiler, with parameters pointing to "...\Cypress\EZ-USB FX3 SDK\1.3\firmware/u3p_firmware/lib/fx3_profile_debug/cyu3lpp.a" (and others like that).

However, in my full-install of the FX3 SDK, in the ...firmware/u3p_firmware/lib/ folder there are just two variants of those libs: fx3_debug and fx3_release; no sign of the fx3_profile_debug !!.

From where can I get those "Profiling enabled" build of the FX3 libraries, please ?

Thank you.

Hi,

Is there any example source of USB Sound Card (MIC + Speaker) as a single project for CX3?

I am trying to design a new board with CYUSB3014-BZXI and with type A usb3 interface.
From SuperSpeed Explorer Kit Schematic.dsn I notice the STDB_SSRX- Pin of TypeB USB3 interface is connected to net SS_RX_P and the STDB_SSRX+ Pin of TypeB USB3 interface is connected to net SS_RX_M, which is mismatched. then I realized this design that exchanges signal between differencial pair make the PCB layout efficient and improve the signal integrity.
My question is whether the SS_TX_P/M could be exchanged likewise, whether the D+/- could be exchanged likewise?

thank you very much!

Hi,

Does FX3 device go to suspend mode after 3ms of inactivity on the bus?

Is there any documents about it?

https://blogs.msdn.microsoft.com/usbcoreblog/2011/05/10/demystifying-usb-selective-suspend/