USB superspeed peripherals Forum Discussions
Hello.
I use an example "uvc camera" - denebola. it works well.
But on some computers, when connected to a USB3 port, it is defined as a USB2 device.
Tell me, why does this happen?
Is this the wrong setting of my computers or camera? What can be done?
Show LessHi All,
I'm running my FX3 chip in conjunction with a cyclone FPGA, using the SlaveFIFO firmware. When i try and use the BulkOutEndPt.Xferdata to write data to my FPGA it seems to work fine most of the time. However if the number of words written is specified as 128,256,512,1024... ect then the DMA flag to begin my FPGA FIFO state machine, doesn't trigger. Its also worth noting that, if i then proceed to do a read, the 512 (or other specified length) write will happen then the DMA flag is triggered.
Cheers
Show LessIf I configure the MIPI block as RAW10 (as shown in the code below), but the GPIF bus is set to 8 bits, what will happen?
My guess is only the first 8 bits of each pixel get sent.
i.e. Camera sends this info for each pixel: Pix[9:0]; MIPI block sends to GPIF only Pix[7:0]
Is this correct?
MIPI configuration:
CyU3PMipicsiCfg_t cfgUvc1080p30NoMclk = {
CY_U3P_CSI_DF_RAW10, /* dataFormat */
2, /* numDataLanes */
1, /* pllPrd */
62, /* pllFbd */
CY_U3P_CSI_PLL_FRS_500_1000M, /* pllFrs */
CY_U3P_CSI_PLL_CLK_DIV_8, /* csiRxClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_8, /* parClkDiv */
0x00, /* mclkCtl */
CY_U3P_CSI_PLL_CLK_DIV_8, /* mClkRefDiv */
1920, /* hResolution */
0x01 /* fifoDelay */
};
GPIF configuration:
status = CyU3PMipicsiGpifLoad(CY_U3P_MIPICSI_BUS_8, ES_UVC_DATA_BUF_SIZE);
Show LessHello.
Please, tell us how the communication and initialization of the device are going on USB3.
For example: initial Hight speed features after detect connection Full speed device.
How does it device recognize that it is connected to port USB3 or to port USB2?
And how does the computer determine that the device USB3 is connected to its ports or USB2 device?
Where it can be read?
How does this happen in FX3 / CX3?
Show LessGPIF II - FPGA interface
GPIF is sychronous master 8bit multiplexed address data
Address is 24 bit, data is 32 bit
Clock can go in either direction
Output 3 controls signals to FPGA
ALE - address latch enable, asserted low
DEN - data enable for reads and writes, asserted low
LWR - local write, high for writes, low for reads
ALE, A[23:16]
ALE, A[15: 8]
ALE, A[ 7: 0]
WAIT - if read operation LWR = 0
DEN, D[31:24]
DEN, D[23:16]
DEN, D[15: 8]
DEN, D[ 7: 0]
..
Repeat data transactions if burst, address auto increments
Show LessHi...
I've been modifying the SRAM_FX3 example in order to write file to an external SRAM. When I read the data back from the SRAM... the data seems to be repeating every 8192 bytes. I was told to first read 8192 bytes and the write it to SRAM and repeat it again and again. I'm new to this and am not entirely sure how to achieve this.
I've attached my SM here. I've not made any other changes to the firmware.
Thank you.
Prav
Show LessHello,
I am using cyusb3035 fx3s,i have interfaced fx3s with two spi flash(same specification and separate chip select) through spi interface.
one flash is for booting the fx3 and other is for data storage.can i interface fx3s with two spi flash?will it cause problem for booting if i do?let me know.
thank you,
Show LessOur device dropped frames after extending the long line. So we want to measure The rate of USB3.0 transmission of the 1080p@30fps's YUV image before extending the long line and after extending the long line. Can you offer a real measurement data or measuring method?
Show LessWhat state of fx3-gpio pin, during power up before firmware upload?
Thanks!
你好,之前有在my case 問過這個問題,貴司fae是回覆要再確認,後來就沒消息了。
想再問,是否已經幫我確認這個問題了。
當FX3一上電後,直到我們的firmware進入成功控制住fx3前,這一段時間gpio的狀態。
請協助確認,感謝!~
Show Less