USB superspeed peripherals Forum Discussions

Hello!

I use Cypress FX3 in my design, so I've tested it with Stream In and Out examples. It works good with precompiled .img files and with rebuilt files too.

The loopback example works only when I load original .img file from Cypress. So, when I rebuilt that example project without any changes, it stops to work.

It looks like data output is OK, but there is no input data. As I discovered with Chipscope, the FLAGC never goes high, so FPGA FSM stucks on waiting.

Is it known problem? What should I change to fix it? I suppose, bug is somewhere in GPIF part.

Many thanks for help!

With regards,

Maksim

Hi, everyone:

     I get a problem with FX3 GPIF port.

     According to my understanding，a P to U DMA manual Channel will commit data to Host in follow two conditions:

     1. one buffer filled

     2. PKTEND became low

     In my test, I control the PKTEND in FPGA, and the last data packet is not  equal to the buffer size , sometime HOST can receive the last packet, but sometime can not, until the buffer size that include the last packet filled with the next fram data packet. I am sure the FPGA prroutine  is fine, it seems like the FX3 didn't respond the PKTEND.

     Are there any suggestions? Or are there any other way to control the condition that commit data?

Hello

We are understanding that the operating frequencies supported are 400 kHz and 1 MHz when VIO5 is 1.8 V, but the customer said that they want to use I2C bit rate as 100kHz when VIO5 is 1.8V.

Is it possible or not?

Best regards

Arai

Hi！

CyU3PDmaChannelConfig_t    CyU3PDmaMultiChannelConfig_t  each have parameters size。

CyU3PDmaChannelConfig_t    AA;

AA.size =1024;

AA.count = 8;

CyU3PDmaMultiChannelConfig_t BB;

BB.size =1024;

BB.count = 8;

In the AA,the DMA total size is 1024*8  and each buffer size is 1024.

In the BB,the DMA total size is 1024     and each buffer size is 1024/8=128.

Whether I understand correctly or not？

Hi all,

I have one problem in 32 bit GPIF. I am using FX3 in 32 bit GPIF mode. Since I was used 32 bit GPIF I can't use the default uart line (GPIO 48) for transmit the data. So I used SPI line (MISO line (GPIO 55)) as uart TX. For my application, I need to set SPI line (uarrt tx) initially as Pull UP (high). So I configured this by using CyU3PDeviceGpioOverride() function. But after sometime I need to use this GPIO as UART TX. Is there any possible ways to do this?.  I tried one way, Initially I configured the UART Tx (GPIO 55) as GPIO by using CyU3PDeviceGpioOverride() function and after sometime I disable that GPIO using CyU3PGpioDisable(). But it was not waorking. if any knows the answer please reply this question. Thanks in advance

Hi,

no matter what I do I get a red badge (error/warning) next to Output Pixel Clock in the " CX3 MIPI Receiver configuration" tool.

The currently calculated value is 127.20MHz

The min value is 110.88, The max value is 100. The max value is smaller than the min!

Could you please provide guidance how the min&max can be influenced?

Hello,

I'm trying to create an application which starts a SPI DMA transfer of 200 bytes every time there is a positive edge on one of the GPIO pins. Right now, I am polling the pin using CyU3PGpioGetValue and starting the DMA transfer on the positive edge by calling CyU3PSpiSetBlockXfer. However, this does not provide the speed that I need for my application, and the RTOS thread manager interrupting the execution of my application thread occasionally causes the application to miss the edge. I tried configuring a GPIO interrupt handler using the Api provided in cyu3gpio.h, but was unable to get CyU3PSpiSetBlockXfer to run inside of the ISR, as it seems like some API calls cannot be called within an interrupt handler. Is there any way to directly set the DMA controller to read SPI data in on an interrupt, or to allow for running a SPI transfer inside an ISR?

Thank you for any insight.