USB superspeed peripherals Forum Discussions
Hello colleagues. in our development, the CYUSB3014 is used with the CC controller - PTN5150AHX and the switch PTN36043BX. When turned on, the switch and the chip determine that they are connected on the Super Speed, but in reality the connection switches to USB 2.0 after a timeout. For verification current USB connection speed I use CyU3PUsbGetSpeed() immediately after the start and periodically in the background. What to do to make the connection at USB 3.0
Show LessHi,
When plug in USB cable, system can find FX3 device, but shows driver is not installed, several seconds later, device will disappear from Windows Device Manager.
System is Windows 10 Pro with latest update.
SDK 1.3.4.
How to fix this?
Thanks!
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I am tying to find:
GX3 Windows Production Test Tool
GX3 EEPROM Configuration Utility
GX3 EEPROM Programming User Guide
I have the CY4702 GX3 Reference Design Kit, but can't find any of the tools referenced in the documentation.
Thanks,
Greg Guchanan
Show LessHello,
I have an application using the FX3 chip CYUSB3014 and I have a question about the logic core power:
The VDD pins of the FX3 receive 1.2V from an external supply to power its logic core. However, if the FX3 is configured (via firmware) to work on bus power mode instead of external power mode, does the FX3 provides power to the logic core (VDD ) internally (by stepping down the 5V USB bus power with built-in regulators)?
The reason I ask is because I probed the 1.2V rail that supplies power to the FX3's VDD pins on my application and I read 0 Amps. So, I guess that if the FX3 is not taking power from the 1.2V external power supply, it may be getting it internally from the 5V input on the USB bus, which is directly connected to the FX3.
Thanks!
Show LessHello everyone,
I read in the programmer's manual (section 3.6.2) that one can change the way the FX3 firmware deals with receiving a NACK from an I2C slave. For example, if I wanted to change what happened when an address match did not occur (therefore receiving a NACK), where would I find the code? Any help is much appreciated. Thanks.
Show LessI am trying to manually compile the SF_loopback.img, SF_streamIN.img and SF_streamOUT.img which are included in the AN65974 project zip file provide at this link:
All the pre-compiled images seem to work fine with the FPGA statemachine that is provided. I need to change a few parameters in the images so I have recompiled the C code in eclipse, but the header in the GPIF II project that was provided is for a 16 bit interface. I changed the interface to 32 in the GPIF II project and confirmed it in the newly generated header file. When I load this version of the image onto the FX3 SuperSpeed Explorer Kit it says, "Download Successful" and then the interface disappears and will not reappear until I restart the FX3 board. If I set CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT equal to 0 indicating a 16 bit interface then the board loads fine. The interface remains after the image is downloaded. The problem is that I need a 32 bit interface. Is there anything I could be missing?
I just want to recompile the images manually that are provided in the AN65974 project zip file (which are 32 bit) and I cannot figure it out.
Thank you in advance.
Show LessHi.
I'm having a problem configuring the GPIO pins on my FX3. Specifically, the CyU3PDeviceConfigureIOMatrix() call returns CY_U3P_ERROR_BAD_ARGUMENT whenever I set any of the bits in io_cfg.gpioSimpleEn[0].
Some details:
The code is as follows:
CyU3PIoMatrixConfig_t io_cfg;
CyU3PMemSet ((uint8_t *)&io_cfg, 0, sizeof(io_cfg));
io_cfg.isDQ32Bit = CyFalse;
io_cfg.s0Mode = CY_U3P_SPORT_INACTIVE;
io_cfg.s1Mode = CY_U3P_SPORT_INACTIVE;
io_cfg.useUart = CyFalse;
io_cfg.useI2C = CyFalse;
io_cfg.useI2S = CyFalse;
io_cfg.useSpi = CyFalse;
io_cfg.lppMode = CY_U3P_IO_MATRIX_LPP_DEFAULT;
/* Enable GPIOs needed for FPGA programming */
io_cfg.gpioSimpleEn[0] = 0x00000000 | (0x1 << (GPIO_FPGA_DIN))
| (0x1 << (GPIO_LED_ORANGE));
io_cfg.gpioSimpleEn[1] = 0x00000000 | (0x1 << (GPIO_FPGA_PROG_L - 32))
| (0x1 << (GPIO_FPGA_INIT_L - 32))
| (0x1 << (GPIO_FPGA_DONE - 32))
| (0x1 << (GPIO_FPGA_CCLK - 32));
// io_cfg.gpioSimpleEn[0] = 0;
// io_cfg.gpioSimpleEn[1] = 0x01E00000;
io_cfg.gpioComplexEn[0] = 0;
io_cfg.gpioComplexEn[1] = 0;
status = CyU3PDeviceConfigureIOMatrix(&io_cfg);
That last line returns CY_U3P_ERROR_BAD_ARGUMENT if anything other than zero is present in io_cfg.gpioSimpleEn[0] (as veried by uncommenting the line that clears the value). GPIO_FPGA_DIN and GPIO_LED_ORANGE are 14 and 23 respectively. All the other defines are over 32.
What am I missing here to be able to use the low pins as GPIO pins?
Thanks,
/Franck
Show Less1. I add a new sensor ov9281 that support raw10 mipi data in cyusb3064, but i find CX3 DMA cannot receive mipi data, No access to the CyCx3AppDmaCallback() function.and the mipi end can be measured with data,Why can't receive data?
Below is my mipi configuration.
/* ov9281_RAW8_720p : 800p */
CyU3PMipicsiCfg_t ov9281_RAW8_720p =
{
CY_U3P_CSI_DF_RAW8, /* CyU3PMipicsiDataFormat_t dataFormat */
2, /* uint8_t numDataLanes */
2, /* uint8_t pllPrd */
89, /* uint16_t pllFbd */
CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */
CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t parClkDiv */
0, /* uint16_t mClkCtl */
CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */
1280, /* uint16_t hResolution */
50 /* uint16_t fifoDelay */
};
we measured The G6 and H5 find no signal ,it is looks like MIPI-CSI2 config problem?
Show LessAttempting to interconnect Broadcom 8 port BCM53128 to the Cypress CYUSB3610. Want to attempt to do a transformerless interconnection (with R & C’s), or perhaps a single 1:1 transformer instead of the traditional phy transformers since these are both co-located on the PCB board.
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