USB superspeed peripherals Forum Discussions
Hi,
SRAMMaster example GPIF II project has a separate start state START1 and compile passed.
Add the same START1 to my project. Why tool reports error?
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Hello sir ,
i have to generate a clock out pulse on fx3 pin using pwm of frequency 24 MHZ with 50% duty cycle for camera module ,also i have merged complexgpio example firmware with uvc .my question is in that complexgpio example they have set period as (201600 - 1) and threshold as (50400 - 1). unable to understand how these values are taken.please help.
Thanks
Manisha
Show LessHello..
I just want to confirm if USB3014 SPI boot is possible in DQ32 mode..
According to datasheet, SPI port can't be used in DQ32 mode.. but I think boot from SPI is possible.. Am I right?
Best Regards,
Show LessHello,
i have a couple of question regarding the FX3 GPIF Interface. I plan to use a synchronous 32 Bit Interface to the FX3 with a 100 MHz clock. I hope i can use the firmware provided with AN65974 with very little modifications.
My first question is on the polarity of the "Thread_X_DMA_Ready" and "Thread_X_DMA_Watermark" flags: It seems that you have to wait until the the flag is deasserted before reading/writing. Is that correct? This seems very unintuitive for a "ready" flag. I plan to configure all flags with active low polarity and initial value low, and then wait with reading/writing until i see a high level on the line.
The next question is regarding partial flags: With a 100 MHz Clock, i can't meet the setup and hold times on the flag signals. To fix this i plan to treat the flags as asychronous signals and use snychronizers in the FPGA to make sure things are stable. That introduces a lot of additional delay on the flags, so i hope i can the following scheme:
Since data should always be written and read in bursts of 1 kB, i hope i can just use watermark flags with a watermark level of 255. If i see a high level on the flag (deasserted) i can read/write a burst of 256 words. Shortly after starting the burst, the flag should change or not. When i'm finished with the burst, the flag should should show if i can start another burst, regardles of all the delays. Is that sensible? I'm afraid of +-1 erros on the watermark level, but 255 seems like a sensible value.
My final question regards (potential) bugs with the watermark flags: I found the attached memo in this post: https://community.cypress.com/message/70337#70337 . It mentions problems using only the watermark flags in the way i described above. I hope i can use the following workaround: I would just wait initially until the Thread_3_DMA_Ready (Thread 3 is USB->GPIF) flag goes high (deasserted) for the first time, before reading or writing using just the watermark flags. Judging by the waveform in the memo, that should fix the described problem in the USB->GPIF direction. Do you thing this approach will work?
I also wonder if that workaround fixes the described problem in the GPIF->USB direction. And will the workaround "survive" if there is a USB reconnect?
Regards,
Markus
Show LessDear all,
I want to ask whether the GPIF II module of CX3 can be customized? We need to modify some parameters of the state machine in the GPIF II module,
such as <data_count > and so on.
Thanks!
Show LessHi,
Can someone point me to the right address when it comes to fx3 cpp liner script file definition? By looking at the programmers manual, I wasn't able to understand what do C++ Exception Handling and Runtime Compiler heap do and how big they need/could be?
Default fx3cpp.ld (C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\common\fx3cpp.ld describes following outline
Descriptor area Base: 0x40000000 Size: 12KB
Code area Base: 0x40003000 Size: 256KB
Data area Base: 0x40043000 Size: 20KB
C++ Exception Handling Base: 0x40048000 Size: 32KB
Runtime Compiler heap Base: 0x40050000 Size: 32KB
Driver heap Base: 0x40058000 Size: 32KB (Update cyfxtx.cpp when changing this)
Buffer area Base: 0x40060000 Size: 128KB (Update cyfxtx.cpp when changing this)
Obviously I'm stuck with code size and I cannot fit into given 512KB anymore.
Tips welcome!
Marko
Show LessHi,
I'm transferring data between my FPGA and the FX3 using the GPIF interface, I'm making bulk transfers with DMA Buffers of 1024 bytes, there's no problems here.
Now, I'm trying to make short packet transfers (with short packets I mean that the DMA buffers sometimes are not completely full and I'd like to transfer the data in the buffer partialy full). I'm using the COMMIT action in the GPIF designer for this and using the Cypress Control Center Application for testing, actually, I'm receiving the short packets but for every short packet received I'm also receiving a Zero Packet.
Can anyone tell me why is that? It can be avoided? If yes, how?
I think is important to say that in my interface the FX3 is the master and the FPGA is the slave, I'm using AUTO DMA Channels between the P-Ports and the USB-Ports and for now I'm just trying with Read Transfers (this mean a FIFO is partialy full in the FPGA and the FX3 is supposed to read it).
Thanks!
Ian.
Show LessHi all,
I am working on Cypress FX-3 project. I created 3 end point ( One Bulk out endpoint and 2 bulk in endpoint).
1. Bulk in end point(0x01) is socket is CY_U3P_UIB_SOCKET_PROD_1.
2. Bulk out end point(0x81) is socket is CY_U3P_UIB_SOCKET_CONS_1.
3. Bulk out end point (0x82) is socket is CY_U3P_UIB_SOCKET_CONS_2.
is this configuration is correct ? how we can give end point address like 0x01,0x02, 0x81,0x82 etc..?.
Thank you
With Regards,
Thrimurthi M
Show LessHello.
I use FX3S and try to work with MMC card connected to S0 port. In my test function I wrote the next loop
for(i=0;i<10;i++)
{
status=CyU3PSibReInitCard(0);
if(status != CY_U3P_SUCCESS)
{
break;
};
};
As I can see that the loop execute only 4 times. And after 5 loop it function return error code 0x68.
But, If I change "useDdr" field in the structs CyU3PSibIntfParams_t for function CyU3PSibSetIntfParams and set this field=CyFalse i have no more problems. The test loop execute 10 time correctly.
The MMC card wich I use is supporting DDR.
How I can solve this problem?
Show LessHi,
I'm trying to develop my own GPIF interface using the FX3 as a master and a Slave FIFO in my FPGA with the HSMC interconnect board, based on the examples in the SuperSpeed Design book and the AN65974 application note.
First, I'm trying to write and read to/from the Slave FIFO using separated projects.
- I'm trying to read data from the FPGA, apparently, the DMA buffer where the data it's written get's filled correctly but when I try to take out the data with a bulk-in transfer in the host-pc with the USB Control Center I get the timming error and zero data... Maybe I'm configuring wrong the Endpoint and the USB consumer socket for that DMA Channel (it's configured in AUTO mode), how's the connection of that USB consumer socket with the Endpoint-in that host-pc is getting data from? Any help?
- Also, seems like the writing process (getting data from the host and write it in the FPGA) is okay, but in the examples of the book is written that drive a GPIO signal takes two clock cycles, so I have to wait two cycles to drive data after driving or assert the WR signal, using the SignalTap-logic analyzer tool of Quartus it seems this latency does not exist and I lost the first two data words, why?
- What's the best manner to drive the clock signal from the FX3 to the FPGA?
Thanks for your attention!
Ian.
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