USB superspeed peripherals Forum Discussions
Hi,
I am trying to write to the Slavefifo which is then read by FX3.I am following the timing diagrams as per AN65974 Application Note.But in logic analyzer,the signals are not triggering and coming as attached.Why the signals are not triggering?
Regards,
Srujana.
Show LessHi,
I am using PACTRON'S FX3S FPGA Dev Board REV-C and cypress EZ-USB SUITE. My question is
1.How to see the consumed memory after build the project?
2.If I build the code this error occurred region `DATA' overflowed by 12156 bytes. `.bss' will not fit in region `DATA' .So I change the fx3.ld file and I update the CY_U3P_MEM_HEAP_BASE in cyfxtx.c file. In fx3.ld file I update sys_mem and data like this:
MEMORY
{
I-TCM : ORIGIN = 0x100 LENGTH = 0x3F00
SYS_MEM : ORIGIN = 0x40003000 LENGTH = 0x2D000
DATA : ORIGIN = 0x40030000 LENGTH = 0x8000
}
But still the error occurs. So what I should do to solve the error?
Thanks & Regards
S. Ravi Chandrika
Show LessHi,
Can someone confirm if hardware strapping is required for JTAG pins?
In datasheet it is mentioned that JTAG TDI, TMC, and TRST# signal has fixed 50k internal pull-up resistor and TCK has fixed 10k pulldown resistor
Thanks,
Menaka
Show LessHello dear Cypress community,
I recently bought a J link V8 probe for JTAG debugging on CX3 RDK denebola development kit from e-con Systems.
The problem is that I can't reach the debug interface. I followed the steps to set up the debug configuration :
But with this configuration I have the following error :
I also tried to change the JlinkGDBServer.exe for the JFlash.exe, and with that configuration I reach the loading for launching the debug interface, but it remains stucked at 62% :
On stack overflow they say that this is a typical bug with the CDT plugin of Eclipse.
Could you help me to fix that problem please ?
Best regards,
Vivien
Hi,
The image from DDR3 is sent to FX3 P-Port,The size of image is 640*480 and i am using GpifToUsb firmware.For transferring image from DDR3 we are using Xilinx SDK.
The problem is after sending image from DDR3 ,i am trying to see data in control center using IN endpoint but the data transfer is failing with error 997.
#define CY_FX_DMA_BUF_SIZE (16384)
#define CY_FX_DMA_BUF_COUNT (7)
My first question is there any problem with configuration of size on both ends i.e..., Are they in Sync?
My second question is either the problem is with DDR3 side or FX3 side?
Regards,
Srujana.
Show LessHi,
i want to transfer some bytes of data from FX3 to DDR3.For that my application is
FX3 -----> FX3 ------> FPGA
(U-Port) (P-Port) GPIF ii
I am using Slavefifosync firmware and modified to meet my application.I am able to transfer data from U-Port to P-Port of FX3.
My question is how to transfer data from P-Port of FX3 to FPGA(Zynq side).
Regards,
Aswini.
Show LessI am trying to create a fx3 slave application with a full and empty flag that is used with an fpga. The fpga assumes the role of master. I programmed the fx3 with the cypress slavefifosync example. However, I don't see any full or empty behavior that I would expect to see based on the user guide timing diagram. The fx3 example project has 4 flags one of which goes high when I write test data to the endpoint using the usb control center application. The flag never goes low even though I am reading the fifo through a gpif interface from my fpga. What am I missing? Are the full and empty flags even part of the slavefifosync example?
Show LessHi!
We have developed a USB 3.0 camera with the FX3 kit as the basis. Occasionally, in some cameras, we get the FX3 automatically switching to Serial MFG mode instead being enumerated as a Composite Device in Device Manager in Windows 10 x64. This happens unpredictably, and may happen once in 2-14 days. Can anyone help with what could be the potential cause of this problem, and what we need to do to resolve this?
Thanks and Regards,
R A
Show LessHello,
I use CyU3PDmaChannelCreate() create 3 dma channel:
(1)CY_U3P_PIB_SOCKET_0 as producer and CY_U3P_CPU_SOCKET_CONS as consumer socket.
(2)CY_U3P_PIB_SOCKET_1 as producer and CY_U3P_CPU_SOCKET_CONS as consumer socket.
(3)CY_U3P_CPU_SOCKET_PROD as producer and CY_U3P_UIB_SOCKET_CONS_3 as consumer socket.
for above 3 dma channel, I config CyU3PDmaChannelConfig_t struct param : size = 32768, count = 2, dmaMode = CY_U3P_DMA_MODE_BYTE.
And I config same callback function for (1) and (2) dma channel.
In DMA callback, I get buffer by CyU3PDmaChannelGetBuffer(), then use CyU3PDmaChannelCommitBuffer() to send buffer. But when I get buffer for the fourth time, CyU3PDmaChannelGetBuffer() return error code 0x45. What my problem?
I also have another question: what dose CyU3PDmaChannelDiscardBuffer() do? Should I use CyU3PDmaChannelDiscardBuffer() after commit buffer?
Show LessHello,
I have a problem while trying to build the CX3RDK_OV5640 project. I followed each step of the firmware build manual for See3CAM_CX3RDK from e-consystems, but I still get an error in the end which is the following one :
That needed variable is located in the "CX3OV5640Lib.h"
And that file is also included in the CX3RDK_OV5640 project :
So it seems that the file is not correctly included in the project, but then I don't know how to proceed.
Could someone help me to fix that bug please ?
Thank you.
Vivien
Show Less