USB superspeed peripherals Forum Discussions
Dears
请问USB3014的工业级与商业级是互相兼容的吗?
我们之前生产,一直用商业级:CYUSB3014BZXC。本批次生产,因为商业级断货,更换为了工业级:CYUSB3014BZXI
结果,本次生产反馈,出现了USB通信异常问题(打开usb的设备驱动和初始化握手失败了)。
我们这边听说过有的公司在将商业级换成工业级时出现过异常。
我们之前的产品,都是商业级,已经很稳定了。这次批量换成工业级,就出现了问题。
我们装了20台机器,有4台出现了USB通信问题。我们也在抓取一些信息。
请问你们的客户遇到过这种商业级跟工业级不兼容的问题吗?
I would like to know why DMA watermark in FX3 code does not tally with GPIF implementation for both GPIF_Example8 and GPIF_Example9 in "SuperSpeed Design Examples V1.2.1"?
GPIF_Example8
CyU3PGpifSocketConfigure(2, GPIF_PRODUCER_SOCKET, 8, CyFalse, 1);
POSTREAD012 RepeatCount = 2
GPIF_Example9
CyU3PGpifSocketConfigure(3, GPIF_CONSUMER_SOCKET, 7, CyFalse, 1);
POSTWRITE012 RepeatCount = 2
Show LessHi all,
I'm modifying the mass storage example code for the FX3 to include an addtional DMA cannel. This additional DMA channel has the same producer socket id as the mass storage out one. I'm getting a channel create error in my last dma channel creation. My question is , Is it alright or not to create tow DMA channels with the same producer or consumer socket id.
Any help appreciated.
Here is the source code.
The first 3 dma channels are fine. error is created in the fourth one, This has the same producer socket id as the first one( ie CY_U3P_UIB_SOCKET_PROD_1).
void
CyFxMscApplnDmaInit (
void)
{
CyU3PDmaChannelConfig_t dmaConfig;
CyU3PReturnStatus_t status;
glMscCbwBuffer = (uint8_t *)CyU3PDmaBufferAlloc (1024);
glMscCswBuffer = (uint8_t *)CyU3PDmaBufferAlloc (1024);
glMscDataBuffer = (uint8_t *)CyU3PDmaBufferAlloc (1024);
glMscCtrlBuffer = (uint8_t *)CyU3PDmaBufferAlloc (32); /* MRB look at making this smaller for efficiency later?*/
if ((glMscCbwBuffer == 0) || (glMscCswBuffer == 0) || (glMscDataBuffer == 0) || (glMscCtrlBuffer == 0)) /* MRB modified */
{
CyU3PDebugPrint (4, "Failed to allocate scratch buffer\r\n");
CyFxAppErrorHandler (CY_U3P_ERROR_MEMORY_ERROR);
}
/* Both DMA channels are created with SuperSpeed parameters. The CyU3PSetEpPacketSize () API is used
to reconfigure the endpoints to work with DMA channels with large buffers. */
dmaConfig.size = 1024;
dmaConfig.count = CY_FX_MSC_DMA_BUF_COUNT;
dmaConfig.prodSckId = CY_U3P_UIB_SOCKET_PROD_1;
dmaConfig.consSckId = CY_U3P_CPU_SOCKET_CONS;
dmaConfig.dmaMode = CY_U3P_DMA_MODE_BYTE;
dmaConfig.notification = CY_U3P_DMA_CB_RECV_CPLT;
dmaConfig.cb = CyFxMscApplnDmaCb;
dmaConfig.prodHeader = 0;
dmaConfig.prodFooter = 0;
dmaConfig.consHeader = 0;
dmaConfig.prodAvailCount = 0;
status = CyU3PDmaChannelCreate (&glChHandleMscOut, CY_U3P_DMA_TYPE_MANUAL_IN, &dmaConfig);
if (status != CY_U3P_SUCCESS)
{
CyU3PDebugPrint (4, "DMA channel create failed1, code=%d\r\n", status);
CyFxAppErrorHandler (status);
}
dmaConfig.prodSckId = CY_U3P_CPU_SOCKET_PROD;
dmaConfig.consSckId = CY_U3P_UIB_SOCKET_CONS_1 ;
dmaConfig.notification = CY_U3P_DMA_CB_SEND_CPLT;
dmaConfig.cb = CyFxMscApplnDmaCb;
status = CyU3PDmaChannelCreate (&glChHandleMscIn, CY_U3P_DMA_TYPE_MANUAL_OUT, &dmaConfig);
if (status != CY_U3P_SUCCESS)
{
CyU3PDebugPrint (4, "DMA channel create failed2, code=%d\r\n", status);
CyFxAppErrorHandler (status);
}
/* Create a DMA Channel for moving control data through GPIF to FPGA */
dmaConfig.size = 32;
dmaConfig.count = 1;
dmaConfig.prodSckId = CY_U3P_CPU_SOCKET_PROD; /* Move from CPU */
dmaConfig.consSckId = CY_U3P_PIB_SOCKET_1; /* To GPIF via socket 1, addressed via Addr A1:A0 "01" from FPGA */
dmaConfig.dmaMode = CY_U3P_DMA_MODE_BYTE;
dmaConfig.notification = 0xFF; //CY_U3P_DMA_CB_SEND_CPLT;
dmaConfig.cb = CyFxMscApplnDmaCbGpif;
dmaConfig.prodHeader = 0;
dmaConfig.prodFooter = 0;
dmaConfig.consHeader = 0;
dmaConfig.prodAvailCount = 0;
status = CyU3PDmaChannelCreate (&glChHandleGpifControl, CY_U3P_DMA_TYPE_MANUAL_OUT, &dmaConfig);
if (status != CY_U3P_SUCCESS)
{
CyU3PDebugPrint (4, "DMA channel create failed, code=%d\r\n", status);
CyFxAppErrorHandler (status);
}
dmaConfig.size = 1024;
dmaConfig.count = 1;
dmaConfig.prodSckId = CY_U3P_UIB_SOCKET_PROD_1;
dmaConfig.consSckId = CY_U3P_PIB_SOCKET_0;
dmaConfig.dmaMode = CY_U3P_DMA_MODE_BYTE;
/* Enabling the callback for produce event. */
dmaConfig.notification = 0;
dmaConfig.cb = NULL;
dmaConfig.prodHeader = 0;
dmaConfig.prodFooter = 0;
dmaConfig.consHeader = 0;
dmaConfig.prodAvailCount = 0;
status = CyU3PDmaChannelCreate (&glChHandleSlFifoUtoP, CY_U3P_DMA_TYPE_AUTO, &dmaConfig);
if (status != CY_U3P_SUCCESS)
{
CyU3PDebugPrint (4, "CyU3PDmaChannelCreate failed4, Error code = %d\n", status);
CyFxAppErrorHandler(status);
}
}
Show LessI have a problem (A) that the USB3.0 link is not connected at high temperature (about 60 to 70 degrees).
The incidence is about 1%.
And I have another problem (B) that FW cannot write in the inspection process during mass production.
*These two PCBs are different it.
I checked the thread below and updated the library.
FX3 Superspeed communication fails on link errors
Then, the problem of (B) board was solved. When using SDK 1.3.4 for the board, a communication error occurred unless the I2C speed was set to 100kHz. However, using this thread's library, it had no problems at 400kHz.
What features did this library update?
The (A) board is still under investigation.
Thanks,
Tetsuo
Show LessHello!
I want to use the FIFO interface (AN65974). I started with the sample code from the application note.
After some modifications to the state machine, I get the error CYU3P_GPIF_ERR_INVALID_STATE.
This is the original state machine:
As I only need to write to the FX3, I removed the READ state, the FLAGC and FLAGD outputs, the address pins and IN_ADDR commands, and the SLOE, SLRD and SLCS pins.
This is the resulting state machine:
Then I realized that DSS_STATE is redundant because it has the same outgoing transitions as the IDLE state, the transitions between IDLE and DSS_STATE have the same condition, and both states have no associated actions.
This is the final state machine:
However, without DSS_STATE, I now get error 0x2000 (CYU3P_GPIF_ERR_INVALID_STATE, "GPIF state machine has reached an invalid state") in the GPIF error callback.
void gpif_error_cb(CyU3PPibIntrType cbType, uint16_t cbArg) {
if (cbType == CYU3P_PIB_INTR_ERROR) {
uint8_t state = 0xff;
CyU3PGpifGetSMState(&state);
CyU3PDebugPrint(4, "GPIF error 0x%x, state=%d\r\n ", cbArg, state);
}
}
According to CyU3PGpifGetSMState, the state machine is in state 1 (IDLE).
Why is this state invalid? When is a state invalid in general? What is the purpose of DSS_STATE?
These state machines uses mirror states. Is this error related somehow?
Regards,
Tobias
Show LessHi
I have created a manual DMA multi channel. When I commit the data to the consumer, sometimes the function fails, returning error code 71. To find the root cause for this, I am wondering what can cause this error code. Does anybody have some more details on this? Thanks.
-Silvio
Show LessDears.
We are designing our system as the following.
Our questions are
- current selected items of "FX3 peripheral used" in GPIF like I2C and spi in accordance with data width 24Bit is correct ?
- If we want to use 32bits data width, is it possible to use SPI and data width 32bits simultaneously ?
Thanks and regards,
WonjinHan
Thanks and best
regards,
Wonjin Han.
Show LessHi Moderator,
I have some follow-up information related to an earlier post in this forum titled "USB data transfer aborts intermittently" and a related 2017 tech support Case # 00359991 for which I need to share attachments privately. I sent an email to cytechsupport@cypress.com but received a notification that this email is no longer in service and my original discussion thread is locked. Could you please unlock the discussion thread and/or provide an email address where I can send in these attachments privately?
Thanks,
Sarad
Original Discussion: https://community.cypress.com/message/254190?et=watches.email.thread#254190
Show Less