USB superspeed peripherals Forum Discussions
We are using the GPIF bus in master mode and clocking out to an external device, but we need to change the speed at which we are clocking it dynamically, i.e. we need to change the PIB clock parameters after the bus has already been initialized. What steps do we need to make sure the GPIF bus doesn't fail to operate if we call CyU3PPibDeInit and CyU3PPibInit.
What is the proper procedure to change the clockDiv aspect of the PIB clock?
We also looked into the TRM but were unable to find appropriate registers to modify to alter the clock divisor.
Any advise or direction (to app note, etc.) would be greatly appreciated!
Show LessHello,
I've got problem with DMA watermark flag for write transfer. From the very beginning it is in it's initial state (active low and initial low), when as per my understanding it should go to low state after I fill buffer with some data. Could it be I have to adjust watermark value in my firmware? Below I attach screen from chip scope.
My FPGA is monitoring state of that flag and when it's changes it state to low allows to write few more words to Fx3 device (based on watermark value in my case watermark is 3)
I've double check my FPGA is monitoring right port (flag uses GPIO21 witch is CTL4 signal in Fx3, G25 in interconnection board).
state machine I use: SyncADMUx(16bit data bus 7bit address bus)
firmware: slave fifo (AN65974; with 2 isochronus endpoint)
I use xilinx FPGA (SP605), and cypress cyusb3-001 kit.
Regards,
Mateusz
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Hello,
I'd like to capture raw12 image on CX3.
My CX3 Receiver Configuration settings are as below:
And Error Messgaes are as below:
CyU3PMipicsiGetErrors
crcErrCnt: 0, ctlErrCnt: 0, eidErrCnt: 0, frmErrCnt: 1, cdlErrCnt: 0
recSyncErrCnt: 0, recErrCnt: 0, unrSyncErrCnt: 0, unrcErrCnt: 0
Could you tell me what's the problem..?
Thanks
Show LessHi, Support Team
I have implemented a UVC appliaction on CX3 board. There is a eeprom on my CX3 board, which stores some paras for calibrating . I would like to send it to PC via USB endpoints . How to implement Endpoint Read/Write in an UVC application?
what should I do on CX3's firmware and how to do in my PC software? Should I install a special driver for it?
Show LessHi,
When my system reboots , it can't find FX3 in linux(I don't have this problem in windows).
I get "No device found", when I run cyusb_linux . (J4 is on). In linux, Fx3 needs to replug after reboot and then I can use it.
I attached the result of lsusb -t before repluging
Thanks
Show LessHello,
I'd like to make a non-uvc project.
I referred to the below link then make a project successfully.
However, I cannot build it with many errors even though I didn't add my own source yet.
I attached my project.
Please let me know what's the problem.
Regards,
Philip
Show LessHi,
According to table 31 in AN76405 "EZ-USB® FX3™/FX3S™ Boot Options" the state of GPIO[17] a.k.a. CTL[0] is "Tristate"
"while the bootloader is executing".
I have some questions related to that table.
Questions:
1) What is meant exactly by "while the bootloader is executing"? Does this table apply when you just plug the EZ-USB board into USB, before loading any firmware, so when the device enumerates as "Cypress FX3 USB Bootloader Device"?
2) The document AN76405 states that the state of GPIO[17] a.k.a. CTL[0] is "Tristate". However, in the situation described under 1) I measure that GPIO[17] is HIGH (in my case 3.3V). Is this correct? My PMODE pins [2,1,0] are low,high,high (USB boot).
The question is relevant, because I use GPIO[17] as RESETN pin for an image sensor. When I first plug in the EZ-USB board into USB, I want GPIO[17] to be LOW to keep the image sensor in reset, before I load the actual firmware over USB. I tried a weak external pull down on GPIO[17] but that did not work, so it is definitely not in a TRISTATE condition as AN76405 suggests...
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I am trying to read from a Mfi chip through i2c using the FX3 SuperSpeed Explorer Kit. The transaction fails. I attached a scope capture showing a read of the mfi chip internal address 0x03. It looks like the chip is setting a short nak after the chip address (0x20). The FX3 i2c peripheral does not seem to care and the nak duration seems to be too short.
Do you have sample code that successfully reads or writes to a mfi chip?
Thanks.
Show LessHere is the thing that I 've bought an CYUSB3KIT-003,and I used it in slave fifo mode. I used FLAGA and set it to gpio_21. As I understand it, gpio_21 is connected to the CTL_4 pin of the board so it should be logic 0 after the board is booted, however , its voltage was about 0.9V.
How is it happen?
Show LessHello,
I'd like to test a custom module which is CSI-2 serial data output (MIPI 2lnae 960 Mbps/lane, D-PHY spec. ver. 1.2 compliant).
is it possible to test it using CX3?
If more information is needed to check it, let me know what it is.
Regards,
Philip
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