USB superspeed peripherals Forum Discussions
Hi,
I finally got all the information from the camera supplier and filled the 'Image Sensor Configuration' tab in the CX3 MIPI Receiver Configuration.
When I switch to the 'CX3 Receiver Configuration' tab, I get the two following errors :
Min/Max values don't make sense so I don't know how to fix these errors ?
I still tried to use the resulting configuration but I only get black screen.
Any idea how to make this interface work ?
Best regards,
SimonP
Show LessHello,
We are upgrading the communication interface of our peripheal from USB2 to USB3 with an FX3 development kit CYUSB3KIT-003.
This peripheal will be connected to a Windows computer.
In our application, the peripheal must receive packets (size below 512Bytes) at the lowest latency possible (<200us).
Is this latency figure achievable with this configuration?
Show LessHello,
I'm working with Denebola kit, so my question is does the data I'm receiving from OV5640 contains header, does uncompressed YUV2 contain header?
Thank you
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According to the CX3 datasheet, on page 8:
Note: REFCLK and CLKIN must have either separate clock
inputs or if the same source is used, the clock must be passed
through a buffer with two outputs and then connected to the clock
pins.
Normally, I design in this clock buffer, but today I tried unsoldering one of the buffers, and shorting across the pads with some wire. Now my CX3 has a single oscillator feeding both the REFCLK and CLKIN pins, with no buffer, and everything seems to work just fine. I'm streaming about 900Mbps of video over USB 3.0, and the 19.2MHz clock waveform looks just fine on the oscilloscope.
Why does the datasheet insist that a buffer is needed. And why does my circuit work just fine without one?
Many thanks
Hugo
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Hello,
I want to use the part CYUSB3065-BZXI in one of the project we are facing, however we need to make a USB link up to 5 meters. May I know which is the maximum USB 3.0 distance you can reach with your device?
Thanks in advance and greetings.
Show LessWorking with two FX3's in a back to back configuration, and I am wondering if I am missing something.
When I push a buffer from Master->Slave, the correct amount of bytes are received with no additional padding added. However, if I send from Slave->Master, GPIF seems to append zeros to fill out the rest of my buffer, which results in me having to use something like the following to remove them, significantly impacting performance.
i = input->buffer_p.count - 1;
while(input->buffer_p.buffer[i] == 0x00){
i--;
}
//input->buffer_p.count always returns 4096 due to GPIF padding. Find actual size, with benefit to full buffers.
CyU3PDmaChannelCommitBuffer (chHandle, i + 1, 0);
Again, this method works, but I would rather use Auto channels for the speed difference, avoiding CPU modification entirely.
I am aware of the 4 byte alignment padding, where sending 6 bytes will add 2 bytes, giving a total of 8 received bytes. This behavior is fine. The issue is when I want to send a short packet, say 84 bytes. When the Master side receives this, I receive a buffer with its count at 1024, and reading out the data shows my 84 bytes, followed by 940 zeros in the packet.
I have tried a variety of settings, but then found that this behavior appears in the provided back to back example, AN87216. Can this be avoided?
As an example:
A transfer from Master->Slave works fine, and the correct number of bytes arrive on the other side.
But from Slave->Master, you can see all of the padding being added.
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Hi
I have to implement a composite super speed USB device on an FX3 that combines a SlaveFifo function (similar to the slfifoasync example) with a virtual UART function (similar to cyfxusbuart example).
I have both functions working separately, i.e. I can create a working SlaveFifo function from a composite device context (EF-02-01) if I leave out the COMx function, and vice versa.
But when I try and instantiate both to operate at the same time, both fail: The COM port does not show up and the SlaveFifo device says "This device cannot start. (Code 10). An invalid parameter was passed to a service or function."
I have tried following the instructions from https://community.infineon.com/t5/USB-Superspeed-Peripherals/How-to-configure-FX3-USB-device-with-multiple-interfaces/m-p/33116
There are a number of things in these posts that do not make sense to me:
1) Step #3: There is no CX3-UVC device listed by the Device Manager. I assumed that it should refer to the Streamer Example Device?
2) Step #15: I do not have an "USB Serial Port" option at this step.
Upon following the instructions to the best of my ability, my laptop semi-freezes up until I uninstall the device.
I am developing on a Windows 10 laptop.
I have not modified any INF files.
I would REALLY appreciate any help/advice.
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Hi,
I observe a strange behavior of GPIO[51] pin in the following scenario:
PMODE pins set for SPI boot and lppMode is set to CY_U3P_IO_MATRIX_LPP_DEFAULT and GPIO[51] is configured as simple GPIO and set to output logic 1.
In such particular case GPIO[51] output is in high-impedance state instead of expected logic 1. Overriding the pin does not help. I also checked the state of I2S, UART and SPI hardware blocks via appropriate registers -- all these blocks are disabled.
However, if PMODE pins are set for USB boot or I2C boot, same firmware works just fine -- GPIO[51] outputs logic 1. Also if lppMode is set to something other then CY_U3P_IO_MATRIX_LPP_DEFAULT, again GPIO[51] is working as expected now even for SPI boot.
And the most weird thing is that if in addition to GPIO[51] another GPIO -- GPIO[57] -- is also configured as simple GPIO, than GPIO[51] suddenly starts working properly (outputs logic 1) in that bad scenario described above.
It seems like booting from SPI lefts something in IO_MATRIX configuration that prevents GPIO[51] from working as Simple GPIO when lppMode is CY_U3P_IO_MATRIX_LPP_DEFAULT. Like that pin is still reserved for some hardware block. Configuring separate GPIO[57] as Simple GPIO resolves IO_MATRIX problems, which is very strange.
Do you have an explanation for such a weird behavior? It looks like a bug in Cypress firmware library related to SPI boot and CY_U3P_IO_MATRIX_LPP_DEFAULT.
Thank you!
--
Sergey.
Show LessHello,
I'm trying to communicate with MPU6050 accelerometer, can anyone tell me how to setup CX3?
what pins should I use for SDA SCL?
if exist please provide me some documents.
Thank you
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