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USB superspeed peripherals

nluong
New Contributor II

Hello,

I am trying to use the FX3 SlaveFIFO in 32-bit mode for automatic DMA transferring. I am able to fill up the buffers and send data to the host, however I noticed half of each of the 32-bit words are missing. This leads me to believe it is operating in 16-bit mode. 

Am I missing a configuration somewhere? Note I have setSysClk400 set to True.

For reference, see main C source file that implements this. The project is a modification of AN75779 firmware, and uses the GPIF design from AN65974.

Thanks,

Nicholas

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1 Solution
JayakrishnaT_76
Moderator
Moderator

Hello Nicholas,

Please answer the following questions so that we can understand the issue better:

1. Please elaborate the following statement in your description:

"however I noticed half of each of the 32-bit words are missing"

Does this mean that if the FPGA (or master) is sending 0xABCDEF00 for one PCLK, then only 0xEF00 is captured by FX3 and the remaining data is lost? Please let me know if my understanding is correct or not. If my understanding is correct, then please let me know how this was confirmed. If my understanding is wrong, then please feel free to correct me.

2. I find that the #define CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT is used to switch between 16 bit and 32 bit interface. But, I find that CyU3PGpifLoad () is always called with the same configuration irrespective of the value of CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT. Please let me know if the second word of GPIF register values is changed based on the value of CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT. This is needed to switch between 16 and 32 bit interfaces. You can refer to the cyfxgpif_syncsf.h in the default Slave FIFO project to understand this change better.

Best Regards,
Jayakrishna

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3 Replies
JayakrishnaT_76
Moderator
Moderator

Hello Nicholas,

Please answer the following questions so that we can understand the issue better:

1. Please elaborate the following statement in your description:

"however I noticed half of each of the 32-bit words are missing"

Does this mean that if the FPGA (or master) is sending 0xABCDEF00 for one PCLK, then only 0xEF00 is captured by FX3 and the remaining data is lost? Please let me know if my understanding is correct or not. If my understanding is correct, then please let me know how this was confirmed. If my understanding is wrong, then please feel free to correct me.

2. I find that the #define CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT is used to switch between 16 bit and 32 bit interface. But, I find that CyU3PGpifLoad () is always called with the same configuration irrespective of the value of CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT. Please let me know if the second word of GPIF register values is changed based on the value of CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT. This is needed to switch between 16 and 32 bit interfaces. You can refer to the cyfxgpif_syncsf.h in the default Slave FIFO project to understand this change better.

Best Regards,
Jayakrishna

View solution in original post

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nluong
New Contributor II

Hi Jayakrishna,

1. Yes your understanding is correct. This was confirmed by sending 0x02020101 on FPGA side, then using wireshark to view the committed buffers. Wireshark shows only 0x0101. Note I have gotten AN65974 working in 32-bit mode and I can see 0x02020101 in this example, so it is not a constraints issue on the FPGA side.

2. This was the issue! I had CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT defined in uvc.c, but not in cyfxgpif_syncsf.h. AN65974 has it defined in cyfxslfifosync.h, which I got rid of when switching to use AN75779 firmware.

Everything works great now. Thanks!

Nicholas

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JayakrishnaT_76
Moderator
Moderator

Hello Nicholas,

We are glad to hear that the issue is resolved!!

Best Regards,
Jayakrishna
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