I have a design with an FX3 as a slave and an FPGA as a master. I would like it if someone can just confirm my understanding of the flags.
If I have an producer socket (data coming into the FPGA) then if the flag is configured as DMA ready, it will be set low when a buffer (say 512 bytes if that is what the buffer is configured) becomes full (512 bytes in the buffer). So the flag would indicate that the buffer is not empty. The flag would go high when the 512 bytes had been read from the buffer.
If I have an consumer socket (data coming from the FPGA) then if the flag is configured as DMA ready, it will be low whilst there is space in the buffer (again if the buffer is 512 bytes). The flag would go high once 512 bytes had been written.
Is this correct?
Here is the clarification from my side:
Let's take two directions of data transfers: one from USB port to GPIF II (P-port) and the other will be from GPIF II to USB port.
When you are looking at first path (U to P) then USB socket will be producer socket and PIB socket will be a consumer socket. Here in this case the DMA flag will be high as long as there is some data in the buffer. It will go low when there is no data.
For P to U path, PIB socket will be producer socket and USB socket will be a consumer socket. Here in this case DMA flag will be high if there is some space in the buffer and it will go low when the buffer is full.
Please let me know if you need any more details from me.
In application note Designing with the EZ-USB FX3 Slave FIFO Interface there is this passage.
The use of a partial FLAG may be completely avoided if the external master can implement a counting mechanism and always write an amount of data that equals the size of EZ-USB FX3’s DMA buffer. The external master should count the data being written or read and ensure that the count does not exceed the buffer size set up when creating the DMA channel. In this case, a full/empty FLAG should be monitored to decide when to begin a transfer
So from the above it seems to indicate that if the flag is ready then a buffer load of data is available. You seem to indiacte the flag would go low once some values are in the buffer. Can you just clarify this.
Here is another passage
For example, if two buffers of 1024 bytes have been allocated to a DMA channel, the full FLAG will indicate full when 1024 bytes have been written into the first buffer. It will continue to indicate full, until the DMA channel has switched to the second buffer. The time taken for the DMA channel to switch to the next buffer is not deterministic, although it is typically of the order of a few microseconds. The external master must monitor the FLAG to determine when the switching is complete and the next buffer has become available for data access.
I have done some tests reading from the interface. It seems as soon as data is put into the buffer the ready flag goes high (not empty). Then if I read the value out the ready goes low 2 clock cycles later. I don't really see how you can do as the application note says regarding just using the ready flag without the partial flag. As unless you were always reading or writing exactly a buffer full of data you wouldn't know when the ready flag would toggle.