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USB superspeed peripherals

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I designed a board using FX3 Peripheral Controller.


I wanted to use a flash SPI to boot and use UART at the same time.
When I made the schematic, I used this file in order to choose which pins I would be using :


I saw that the "16 - bit Data Bus + UART+SPI+I2S" case would fit my design because I'd like to use UART for debugging and SPI for SPI Boot (for the FX3). And I would like to add I2S to my design in the future.


I then received my custom board and I decided to use the cyfxusbuart example (located at Cypress_installation_folder\EZ-USB FX3 SDK\1.3\firmware\serialif_examples\cyfxusbuart). But when I program my board, it appears that the pinout is not the one described in the upper document (the "16 - bit Data Bus + UART+SPI+I2S" pinout). Actually, the pinout probably is the "16 - bit DataBus +UART+GPIO" because I can see the TX and RX on a scope when I probe GPIO[55] and GPIO[56] pins.


Even if the SPI interface is only used during boot, I'd like to have separate lines for each signal from each interface, I don't want to have both interfaces crossed. Because the things that are using UART will see some weird stuff during SPI boot/programming.


I cannot change by board layout because it's a PCB so the pin mapping of the program running on FX3 has to be just like the "16 - bit Data Bus + UART+SPI+I2S".


Can somebody please tell me how to change the program pinout ?

2 Replies
Not applicable

Yes, the cyfxusbuart example has the UART pins on GPIO53-56. 


As you have mentioned, you will need to change the pin map. For this, you need to change the IOMatrix configuration of the device. This can be done by updating the IO matix configuration as follows. Please look for the following snippet in the main function of the code:


io_cfg.isDQ32Bit = CyFalse;
    io_cfg.s0Mode = CY_U3P_SPORT_INACTIVE;
    io_cfg.s1Mode = CY_U3P_SPORT_INACTIVE;
    io_cfg.useUart   = CyTrue;
    io_cfg.useI2C    = CyFalse;
    io_cfg.useI2S    = CyFalse;
    io_cfg.useSpi    = CyTrue;  // made it to CyTrue to enable SPI. If you do this, the the UART pins will be GPIO:28-31;
    io_cfg.lppMode   = CY_U3P_IO_MATRIX_LPP_DEFAULT; //changed this to default to enable all peripherals
    /* No GPIOs are enabled. */
    io_cfg.gpioSimpleEn[0]  = 0;
    io_cfg.gpioSimpleEn[1]  = 0;
    io_cfg.gpioComplexEn[0] = 0;
    io_cfg.gpioComplexEn[1] = 0;
    status = CyU3PDeviceConfigureIOMatrix (&io_cfg);
    if (status != CY_U3P_SUCCESS)
        goto handle_fatal_error;

Not applicable

Thanks for the reply Nishant,


Is there document that shows what is the pin mapping for each configuration. Because it looks pretty random. What is the configuration if I set :


io_cfg.useUart   = CyTrue;
io_cfg.useI2S    = CyTrue;
io_cfg.useSpi    = CyTrue;


Is the pin mapping for this configuration going to look like the "16 - bit Data Bus + UART+SPI+I2S one ?