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Hi,
I am sending data to FX3 GPIF from FPGA in Async mode. Data bus width is 16 bit. I toggle the SLWR in 10MHz, push the data to socket 0, and I am able to read the data in USB PC side using a python script. When I change the speed to around 5MHz (means SLWR strobing not PCLK), I am not able to get any data out of USB. There is no changes in Flag A or B and slwr lines. But everything works as expected if the SLWR strobing happens at 10MHz.
I am using the SlaveFIFO2b example code in my FPGA. I was thinking that in Async mode, SLWR does not depend on speed of the clock. Please let me know what I am missing here.
Solved! Go to Solution.
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Hello,
The problem can be from the interface signals generated from the Master.
Can you please share the logical traces of the flags and control signals from the FPGA.
We have sample FPGA codes in AN65974: https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inte...
Thanks,
Yatheesh
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Hello,
Yes, in asynchronous mode the speed on the clock is independent.
Can you please let me know the size and rate at which the data is being read from the USB host and the size written from the Slave FIFO side (FPGA)?
Are you making any changes to the existing async slave FIFO 2 bit project form the Fx3 SDK?
Thanks,
Yatheesh
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“”Are you making any changes to the existing async slave FIFO 2 bit project form the Fx3 SDK?””
There are changes on the GPIF side, Added code for other peripherals only. We are not changing anything from GPIF side ,we are using the structures provided by cypress for async, only change in there from cypress code is change of flag_a and flag_b conditions to current thread ready and watermark.
""Can you please let me know the size and rate at which the data is being read from the USB host and the size written from the Slave FIFO side (FPGA)?""
We are only getting data from fpga to fx3.Currently with 10MHZ clock we are getting 18 MBps speed.
I made a little changes in the FPGA Code.
Forced the mode to be always stream-in for testing purposes.
ELSIF(clk_100'event AND clk_100 = '1') THEN
-- mode <= mode_p;
mode <= STREAM_IN ; -- FORCE for STREAMING MODE as a test
END IF
------------------------------------------------------
-- FPGA WRITE TO FX3
------------------------------------------------------
-- and let it out only when writing to GPIF (streamin case), otherwise tristate
PROCESS(slwr_n_d, data_out_d)
BEGIN
IF (slwr_n_d = '1') THEN
DQ <= (OTHERS =>'Z');
TP23 <= '1';
ELSE IF (slwr_n_d = '0') THEN
IF(ebi_nwe_op = '1') THEN -- 5MHz speed
--IF(TIMEBASE = '1') THEN -- 10MHz speed
CTL1_SL_NWR <= '1';
ELSE
DQ <= X"55AA";
CTL1_SL_NWR <= '0'; -- Strobe the WR# pin using TIMEBASE as long as slwr_n_d is active
END IF;
END IF;
END IF;
END PROCESS;
I am able to see the waveforms (SLWR# goes low, Flag A &B is up etc…) while writing to socket 0 (faddr <= 00) at 10Mhz speed, but nothing happens at 5MHz speed.
I need to strode the CTL1_SL_NWR, since GPIF is in async mode.
Do you have an example FPGA code for Async modes?
Regards,
GSK
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Hello,
The problem can be from the interface signals generated from the Master.
Can you please share the logical traces of the flags and control signals from the FPGA.
We have sample FPGA codes in AN65974: https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inte...
Thanks,
Yatheesh
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Hi,
I do not see any issues with the interfacing signals. I directly use your example code as given in 001-65974_AN65974 example.
Since I am using it in Async mode, I need to strode the SLWR signal. If I strobe in at 10MHz, I can see the transfer happens from FPGA to GPIF. But when I strobe SLWR at 5MHz, I cant see the data transfer using the same testing method.
Do you have any example code for Async mode?
Regards,
GSK
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Hello,
You can refer to the SlaveFifoAsync example from the FX3 firmware present in the Fx3 SDK.
Thanks,
Yatheesh