Cypress CX3 CYUSB3065 maximum resolution

[MiVu_4817671]

Hello,

Is there any limit in maximum resolution or line length over MIPI interface if throughput is less than 2.4Gbps?

I'm trying to configure CX3 to read images 7992x6000 RAW 10 bits and configuration tool does not give me any errors but I do not receive correct frames. The image sensor can oputput 8000x6000 but as I understand H active needs to be divisible by 24? If I reduce H active to 4000 or less it works, bit once I configure H active over 5000 it does not. Changing V active to lower values does not allow me to increase H active. Bellow are 2 configurations, the first one works just fine. Bellow are snapshots of configuration tabs. I'm using SDK version 1.3.3.

[Rashi_Vatsa]

Hello,

The maximum bandwidth that CX3 can support is limited by the GPIF II block of CX3. As mentioned in TRM it can support till 2.4Gbps. So if you want to use all 4 lanes, then CX3 can support only 600Mbps/lane (300MHz DDR clock).

The maximum input CSI MIPI sensor rate supported by CX3 with 4 data lanes 300 MHz * 2 (DDR - sampling rate) * 4  * 1 bit= 2.4 Gbps.

Please try to configure the CSI clock frequency to <= 300MHz with 4 data lanes. Else the video will not stream properly due to data loss.

On the other hand, if you are only using 2 lanes, then each lane can support up to 1Gbps.

The bandwidth is not limited by the MIPI receiver, but by the GPIF II block inside CX3.

Regards,

Rashi

[MiVu_4817671]

Hello Rashi,

Thanks for the response, but I understood this differently, I think that throughput takes in account FPS also?

So, actual throughput is  7992 * 6000 * 1fps * 10bits = 479.52 Mbps which can be received by GPIF?

I succeed to get frames correctly after a mistake in configuration see bellow. When I set Output parallel clock to 4 it does not work, I still get some frames in desired frame rate, but the size vary and it is never equal to what I expect.

Best Regards,

Milan

[Rashi_Vatsa]

Hello Milan,

The CSI clock needs to be configured such that the input data rate does not exceed the maximum GPIF bandwidth supported otherwise data loss is expected. The GPIF interface supports 2.4 Gbps when the pixel clock is 100 MHz and the GPIF bus width is 24 bits (24*100 MHz).

If the CSI clock is 315 MHz, the input rate will be 315*2*4*1 = ~2.5Gbps

So, actual throughput is  7992 * 6000 * 1fps * 10bits = 479.52 Mbps which can be received by GPIF?

>> Yes, we need to consider the video throughput as well as the CSI clock limitation based on the constraint posed by the GPIF interface.

When I set Output parallel clock to 4 it does not work, I still get some frames in desired frame rate, but the size vary and it is never equal to what I expect.

>> As mentioned earlier, the data loss is expected when the CSI clock is configured as 315 MHz with 4 data lanes. Please configure the CSI clock for <= 300MHz and let me know the results

Regards,

Rashi

[MiVu_4817671]

Hello Rashi,

Minimum CSI clock on my camera is 270MHz. I have tried to set CSI clock to 300MHz and it does work the same as with 315MHz I'm not loosing any frame. Below are 2 configuration where the first one works fine, but the second has an issue and I'm not sure what is happening. Can you shed some light to it? Also, when I increase both Output Pixel Clock and CSI Rx LP <--> HS Clock I get strange frame size, but frame rate is correct.

Working configuration frame rate 30fps, frame size 2813700 B which is exactly 1992*1130*10/8

Do not work configuration

Best Regards,

Milan

[Rashi_Vatsa]

Hi Milan,

From the snapshot, I see that when the pixel clock is configured for 30 MHz the video frame size is as expected but when the divider value is changed to increase the pixel clock to 64 MHz, the video frame is not as expected. Is this right?

If yes, the behavior is strange. We would need to do more test with different CX3 MIPI configurations to understand the problem

- Please configure the pixel clock to a value between 32 and 64 MHz

- Configure the pixel clock to > 80 MHz

- Try changing the Multiplier value to set the pixel clock to 64MHz instead of the Divider value

Please let me know the results (UART debug prints) of this

Regards,

Rashi

[MiVu_4817671]

Hi Rashi,

Yes, you are right. When I change divider it does not work.

When I use a multiplier to configure clock it works, until 130 but for 140 and above it does not work properly.

I have never get it working when Pixel clock was over 80MHz for any configuration.

Best Regards,

Milan

[Rashi_Vatsa]

Hello Milan,

Can you please share the UART debug prints for different tests.

This will help us to know what affect is seen on the frame size when Multipler/Divider is changed.

Also, share the UART debug prints when ixel clock is configured for  >80MHz

Regards,

Rashi

[MiVu_4817671]

Hello Rashi,

Here are 3 configurations, one working and two which do no work.

1. DebugWorksPixelClock32MHz

2. Debug-DoNotWorkPixelClock60MHz

3. Debug-DoNotWorkPixelClock88MHz

Best Regards,

Milan

[Rashi_Vatsa]

Hello Milan,

Please let me know if there are any MIPI errors by enabling the below mentioned debug print seen with the configurations where the streaming is not proper

CyU3PMipicsiGetErrors( CyTrue, &errCnts);

CyU3PDebugPrint(4,"\n\r%d %d %d %d %d %d %d %d %d",errCnts.crcErrCnt,errCnts.ctlErrCnt, errCnts.eidErrCnt, errCnts.frmErrCnt, errCnts.mdlErrCnt, errCnts.recSyncErrCnt, errCnts.recrErrCnt, errCnts.unrSyncErrCnt, errCnts.unrcErrCnt );

Please confirm if the firmware is generated by the CX3 MIPI tool as per the steps mentioned in this KBA Steps to Setup up MIPI CSI Camera Solution with CX3 – KBA225748

Also, let me know if your board has the test points (HSYNC, VSYNC, PCLK) as mentioned in Q10 of this KBA CX3 Hardware: Frequently Asked Questions - KBA91295

Regards,

Rashi

[MiVu_4817671]

Hello Rashi,

Yes, firmware is generated by CX3 MIPI tool as explained in KBA225748.

Yes, I do have test points on my board.

Regarding MIPI errors, even when it does not work there are no error reported

0 0 0 0 0 0 0 0 0

Prod = 114 Cons = 114  Prtl_Sz = 23112 Frm_Cnt = 42 Frm_Sz = 4220136 B

0 0 0 0 0 0 0 0 0

Prod = 114 Cons = 114  Prtl_Sz = 23100 Frm_Cnt = 43 Frm_Sz = 4220124 B

0 0 0 0 0 0 0 0 0

Prod = 114 Cons = 114  Prtl_Sz = 23124 Frm_Cnt = 44 Frm_Sz = 4220148 B

0 0 0 0 0 0 0 0 0

Prod = 114 Cons = 114  Prtl_Sz = 23142 Frm_Cnt = 45 Frm_Sz = 4220166 B

0 0 0 0 0 0 0 0 0

Prod = 114 Cons = 114  Prtl_Sz = 23136 Frm_Cnt = 46 Frm_Sz = 4220160 B

0 0 0 0 0 0 0 0 0

Prod = 114 Cons = 114  Prtl_Sz = 23160 Frm_Cnt = 47 Frm_Sz = 4220184 B

0 0 0 0 0 0 0 0 0

Prod = 114 Cons = 114  Prtl_Sz = 23160 Frm_Cnt = 48 Frm_Sz = 4220184 B

0 0 0 0 0 0 0 0 0

Prod = 114 Cons = 114  Prtl_Sz = 23112 Frm_Cnt = 49 Frm_Sz = 4220136 B

0 0 0 0 0 0 0 0 0

Best Regards,

Milan

[Rashi_Vatsa]

Hello Milan,

I missed one of the information from the description. It seems that you are using SDK 1.3.3.

Please try installing the latest SDK 1.3.4  https://www.cypress.com/documentation/software-and-drivers/ez-usb-fx3-software-development-kit and use the CX3 MIPI Configuration Utility provided with it. Also, build the firmware with SDK 1.3.4 by modifying  the BUILD variable to 1_3_4 ( Project Properties>  C/C++ Build> Build Variable)

Please let me know the results

Regards,

Rashi

[MiVu_4817671]

Hello Rashi,

I have the same behaviour with 1_3_4 firmware SDK.

Best Regards,

Milan

[Rashi_Vatsa]

Hello Milan,

Thank you for the confirmation

Can you please probe the PCLK, HSYNC, VSYNC test points on the board for both cases

1) When streaming is proper i.e. PCLK 32 MHz

2) When the frame size is not s expected i.e. PCLK 64 MHz.

Also, confirm by probing CSI clock that the frequency of CSI clock from the sensor is 300 MHz

As you mentioned earlier that the minimum clock frequency supported by the sensor is 270 MHz, can you try configuring the sensor clock as 280 MHz and let me know the results?

Regards,

Rashi

[MiVu_4817671]

Hello Rashi,

Here is an image with 32MHz clock with CH1 VSYNC, CH2 HSYNC, CH3 PCLK.

Here is an image with 64MHz clock

I do not have an instrument to measure a 300MHz clock. I checked both clocks have correct values 32MHz and 64MHz.

Changing the CSI clock does not change anything. It works on 32MHz PCLK and does not on 64MHz.

Also, I managed to write a custom PC application to capture frames and using test pattern solid image with fixed values for pixels.

I can see some strange pixels 10 pixels periodically 32758-32767 when using 16bit GPIF.

When using 24bit GPIF I have some strange offset and I'm not sure if that is coming from the camera or GPIF block and also strange 12 pixels periodically at 131060-131071.

Best Regards,

Milan

[Rashi_Vatsa]

Hello Milan,

Thank you for the traces

I cannot measure the H blanking, H active time from the traces shared. Could you please let me know the H-Active, H blanking, V active, and V Blanking time from the traces for both the cases

can see some strange pixels 10 pixels periodically 32758-32767 when using 16bit GPIF.

When using 24bit GPIF I have some strange offset and I'm not sure if that is coming from the camera or GPIF block and also strange 12 pixels periodically at 131060-131071.

>> Please confirm if this issue is seen with a test pattern solid image with fixed values for pixels. Was this issue seen for both cases i.e. 32MHZ and 64 MHz PCLK

Yes, it seems that there is some mismatch between the sensor configuration and the CX3 MIPI receiver tool configuration.

Regards,

Rashi

[MiVu_4817671]

Hello Rashi,

For the 32MHz I get following:

H active 25.93us

H blanking 2.063

V active 32.03

V blanking 1.28

For 64 MHz H active is not correct, I do not understand what is the reason (image below) for this while V active is as expected V active 32.02 and V blanking 1.29.

I did not unpacked data from 64MHz since frame size is almost double and I do not know how to interpret that.

Best regards,

Milan

[Rashi_Vatsa]

Hello Milan,

Okay I understand that HSYNC is not as expected hen PCLK is configured for 64 MHz

can see some strange pixels 10 pixels periodically 32758-32767 when using 16bit GPIF.

When using 24bit GPIF I have some strange offset and I'm not sure if that is coming from the camera or GPIF block and also strange 12 pixels periodically at 131060-131071.

>> Please confirm if this issue is seen with a test pattern solid image with fixed values for pixels. Was this issue seen for both cases i.e. 32MHZ and 64 MHz PCLK.

I did not unpack data from 64MHz since the frame size is almost double and I do not know how to interpret that.

>> By this do you mean the above-mentioned problem ( see some strange pixels 10 pixels periodically 32758-32767 when using 16bit GPIF) is seen with 32 MHz PCLK?

Regards,

Rashi

[MiVu_4817671]

Hello Rashi,

Can you put some light on why I have an issue with HSYNC? I still do not understand what I'm doing wrong with 64MHz clock?

Regarding wrong pixels it is on 32MHz, but with different GPIF configuration for solid image with fixed values for pixels. I did not look at data on 64MHz, since frame size is variable and I'm not sure how to interpret data, what are lines since there is almost double data.

Best Regards,

Milan

[Rashi_Vatsa · Accepted solution]

Hello Milan,

The problem seems to be with the CX3 MIPI receiver settings and the  Sensor (MIPI Transmitter) settings.

The HSYNC, VSYNC on the test points are not proper when the sensor settings do not match with the CX3 MIPI Receiver settings.

As shared by you that for pixel clock > 80 MHz the HSYNC, VYSNC is not seen at all, this generally happens when CX3 MIPI receiver settings and the  Sensor (MIPI Transmitter) settings are not in sync.

Please let me know if you have the seen same problem with other resolutions. Are other resolutions working fine?

Please let me know if the CSI clock is in continuous mode or gated mode. Please refer to Q13 of this KBA CX3 Hardware: Frequently Asked Questions - KBA91295

Also, please let me know if the Phy Time Delay value is set in the firmware. This value is calculated by the tool (see in right bottom corner of the MIPI Receiver Configuration) . It must be manually set using CyU3PMipicsiSetPhyTimeDelay ().

This function should be not be called while the MIPI-CSI PLL clocks are active. Either call after calling CyU3PMipicsiSetIntfParams() with wakeOnConfigure set to False (before calling CyU3PMipicsiWakeup() ), or call CyU3PMipicsiSleep() before calling this API.

Regards,

Rashi

[MiVu_4817671]

Hi Rashi,

I have the same situations for 4 tested resolutions. It works on a low pixel clock frequency, even if it should not. For example on resolution 7992x6002 @1fps minimum pixel clock should be 74.20 but I can receive full frames on 72MHz, but not on any above 74MHz.

Is there any API which can give me CSI clock speed detected by CX3?

Best regards,

Milan

[Rashi_Vatsa]

Hello Milan,

Please let me know if there is improvement in using higher Multiplier value (Multiplier of Unit Clock) to increase the pixel clock frequency instead of decreasing the divider value.

Can you try tuning the following parameter keeping the divider values  (Output parallel clock divider & CSI RX Clock divider) same as the earlier working configuration

- Pre divider value

- PLL Out Range

- Multiplier of Unit Clk

Is there any API which can give me CSI clock speed detected by CX3?

>> We do not have API which gives the CSI clock value

Regards,

Rashi

[MiVu_4817671]

Hello,

Rashi, looking at HSYNC and VSYNC helped me find the issue with configuration mismatch between CX3 and my image sensor. It turned out that in image sensor datasheet it was not stated that CSI clock is half of another clock (there was no divider in Clock diagram).

I have one more issue, but I will start another thread.

Thanks,

Milan

[Rashi_Vatsa]

Hi Milan,

Thank you for the confirmation.

Glad to hear that you were able find that the problem was in CSI clock frequency from the sensor which didn't match the CSI clock frequency populated in the CX3 MIPI Receiver Tool

Regards,

Rashi