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Hello,
I have implemented a Slave FIFO interface between the FPGA and FX3.
But it seems like there are some configuration issues. I cannot get the interface working yet.
When ever I use CyU3PGpifGetSMState() API it always gives zero as the current state. When I check in GPIF Designer, the LOGIC_ONE condition is put in between RESET and IDLE states.
Therefore, I think I should not get Reset state. How can this happen? Can someone please explain?
Thank you.
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Hi Pradeepa Senanayake,
Please let su know what are the changes you have made and also what exactly is the issue you are facing ?
Thanks,
Krishna.
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I mean the changes you have made in the SlaveFIFO firmware.
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Hello,
This issue is solved. The issue was related to the connection between FX3 and FPGA. Now it is properly working.