USB low-full-high speed peripherals Forum Discussions

Hi

I have a problem with CY7C68013A. This is the third time that my usb controller was failed and Be destroyed. I really dont know the reason. While my usb work properly and send/recive data suddenly it disconected and failed. After that when I Plug it again to PC  the controller dosn't detected by host in Device manager.

could you please give me a hand and some point to solve this problem.
Is it related to the earthing or grounding ?

Regards

j.sh

Hi,

I would like to support multiple alternate settings for my ISO endpoind.

The question: how can I catch the standard request, in order to respond correctly to the GET_INTERFACE call?

Dear all,

Is that possible the CY7C68013 run a firmware larger than 8KB/16KB? How to compile large firmware code of the CY7C68013 under Keil C environment?

I want to control a LCD and a data acquisition unit by the 8051 of a CY7C68013. Due to a mass of functions for the LCD controlling, the code size of the fireware is larger than the allowed band of the Keil compiler (uVision4), which prompt that "Program Size: data=132.6 xdata=4464 code=5063, Target not created" when I build the project.

As I know, there is only 8 KB code and data RAM in the CY7C68013. Is that possible the CY7C68013 run a firmware larger than 8KB/16KB? And how? How to configure the Keil project? Pls. give me some instructions step by step.

Thanks a lot!

PS: My hardware works well with smaller firmware and a 128 KB EEPROM 24LC128 is connected with CY7C68013  through the I2C. The target setting of my Keil project is shown in the attached figure.

Hi, 

I need to work on CY7C68013A usb high speed micro controller. I am designing my own hardware for small test applications initially, hence I dont have the evaluation kit pack in my hands. 

What is the compiler and development IDE I should use for the developing my applications on CY7C68013A controller .

I triied using Keil uvision compiler and IDE, but it throws the error    

*** ERROR L107: ADDRESS SPACE OVERFLOW

    SPACE:   CODE    

    SEGMENT: ?PR?ISR_SOF?BULKLOOP

    LENGTH:  0016H when I tried to compile the "Bulkloop" example project from cypress. 

Hi,

I am using FX2LP in slave fifo mode for USB integration with the FPGA on a custom board. The USB controller works fine for small to medium transactions. If I try back to back bulk writes (each of 1M Bytes), the controller becomes non responsive. I can see the transactions being posted by the host, but the FPGA never gets any response from slave fifos. The problem suddenly disappears if I try a smaller write. Then for some time, the larger writes will work and again will run into a halt after a few write cycles.

Any suggestions what's going wrong the FX2LP ?

Thanks,

Abhey

Hi, 

I have a USB device designed out of Cy7C680-13A usb high speed controller. The design uses an EEPROM IC to store the device firmware. The address lines for EEPROM is hard wired to 0,0,1 for A2, A1, A0 respectively. 

Using the Cypress tools, can I download any test firmware directly to the usb controller. After testing the device with the test firmware, will the system revert back to the original firmware from EEPROM IC after a hardware reset. 

How can I download the firmware through USB in case I am working on other platforms like ARM9 linux based usb hosts. ? 

Thank You

GIGIN JOSE

Hi.

Recently I designed a small usb key using the CYC68023 IC (marked in the package silkscreen). When I plug it to the usb port in windows 7 it appears in the usb devices list, but its VID/PID doesnt match the correct ones (04B4 - 6813). Instead, it shows 04B4 - 8613... which I found it matches with the CY7C68033 IC! 

The device is shown with the label "Cypress FX2 - No EEPROM (0x8613)"

Using the NX2LP programmer for the 033 part it sees the NAND IC and I can program it, but Windows isn't able to format it correctly.... any clue?

Thanks in advance.

 Hello, I am currently working through Application Note 56377, and I am having some difficulty in setting up the USB drivers for the vendor and product ID's; I am working on Windows 7 x86 with PSoC 5 and CY8CKIT-001.

The error that I am continually running into is changing the product and vendor ID in the .inf file. I am following the tutorial on how to do that, but when I plug in the device, the PSoC is not detected, although my computer does detect that something is plugged into the USB port. When changing the product and vendor ID's, I am using the ones that are setup in the PSoC USBFS, provided in the Application note; is that correct? I am also following the Cypress CyUSB.sys Manual for changing and setting up the drivers. I have the latest version of the Cypress USB Suite.

I have attached the .inf as a text document if anyone is able to look over it and see if there are any errors.

Thank you for your help!

 hi,

I am using Win7 + Suite USB 3.4.7 + 68013A PVX 56 + slave FIFO + (FPGA) Cyclone II,

I use CyConsole input" 1 2 3 4 5 6 7 8 9" , to EP2 , but I read "2 4 6 8" from EP6,

half data lose! anyone can help me ? thanks!

below is my  firmware and verilog code:

=============================================================

// Called once at startup

    CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT

    IFCONFIG = 0xE3; 

REVCTL=0x01;

// 48 MHz internal clock source, drive IFCLK, synchronous slave FIFO mode

  PINFLAGSAB = 0x08;    // FLAGA - EP6 FULL flag

    SYNCDELAY;

PINFLAGSCD = 0xE0;    // FLAGD - EP2 Emtpy flag

    SYNCDELAY;

    PORTACFG |= 0x80;

    EP4CFG = 0x02;               //clear the valid bits on ep4 and ep8

    SYNCDELAY;                 

EP8CFG = 0x02;                

SYNCDELAY;                    

EP2CFG = 0xA2;                // OUT, 512-bytes, 4x, bulk

    SYNCDELAY;                    

EP6CFG = 0xE2;                // IN, 512-bytes, 4x, bulk

    SYNCDELAY;

FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions

    SYNCDELAY;                    // see TRM section 15.14

    FIFORESET = 0x02;             // reset, FIFO 2

    SYNCDELAY;                    //

    FIFORESET = 0x04;             // reset, FIFO 4

   SYNCDELAY;                    //

    FIFORESET = 0x06;             // reset, FIFO 6

    SYNCDELAY;                    //

    FIFORESET = 0x08;             // reset, FIFO 8

    SYNCDELAY;                    //

    FIFORESET = 0x00;             // deactivate NAK-ALL

    // handle the case where we were already in AUTO mode...

    // ...for example: back to back firmware downloads...

    SYNCDELAY;                    //

    EP2FIFOCFG = 0x00;            // AUTOOUT=0, WORDWIDE=0

  // core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's

  SYNCDELAY;                    //

    EP2FIFOCFG = 0x10;            // AUTOOUT=1, WORDWIDE=0

  SYNCDELAY;                    //

    EP6FIFOCFG = 0x0C;            // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0, INFM = 1;

    SYNCDELAY;

=======================================================================================

module fpga_master

(

input clk,

input rst_n,

input flaga, //EP2 empty flag

input flagd, // EP6 full flag

output reg [1:0] faddr,

output reg sloe,

output reg slrd,

output reg slwr,

inout [7:0]fdata,

output led,

output beep

);

(* noprune *)reg [25:0] counter;

assign led =counter[25];

assign beep =1;

reg link = 0; //link控制三态门

(* noprune *)reg [7:0]fdata_reg = 0;

assign fdata = link ? fdata_reg:8'bz;

(* noprune *)reg [3:0] state = 0;

(* noprune *)reg [31:0] recv_count = 0;

(* noprune *)reg [31:0] send_count = 0;

(* noprune *)reg [7:0] fifodata = 0;

always@(posedge clk)

begin

counter <= counter + 26'b1;

end

(* noprune *) reg [7:0] temp[15:0];

always@(posedge clk)

begin

case(state)

0: 

begin

 faddr <= 2'b00;

 sloe  <= 0;                               // IDLE STATE

 link  <= 0;

 slrd  <= 1;

 slwr  <= 1;

 state <= 1;

end

1:

begin

if(flaga == 1) // not empty

begin      

 slrd  <= 0;

 state <= 2;

end

else

begin

 slrd  <= 1;

 state <= 0;

end

end

2:

begin

fifodata = fdata;

temp[recv_count] = fdata;

recv_count = recv_count +1;

faddr <= 2'b10;        // ep6

link  <= 1;

sloe  <= 1;

state <= 3;

end

3:

begin

if(flagd == 1) // not full

state <= 4;

else

state <= 3;

fdata_reg <= fifodata;

end

4:

begin

slwr  <= 0;

send_count <= send_count +1;

state <= 0;

end

default:

state<=0;

endcase

end

endmodule

 Hi

I setup the transfer using the auto-out mode. Everything the PC sends to the device is transferred using GPIF transfer.

Unfortunately, I need to skip the first packet, transmit 300 packets, skip 301 packet, transmit another 300 packets and so on.

In the ISR_Ep2inout I check the packet content and try to ignore it before the setting the GPIF transfer.

The code:

EP2FIFOCFG = 0x01; // manual mode

SYNCDELAY;

OUTPKTEND = 0X82; // skip packet

SYNCDELAY;

EP2FIFOCFG = 0x11; // back to auto out mode, disable PKTEND zero length send, word ops

SYNCDELAY;

Is it any way to skip exactly one packet from EP2 buffer and preserve others intact?