USB low-full-high speed peripherals Forum Discussions

The  http://www.cypress.com/part/cy7c67200-48baxi contains a lot of information about the CY7C67200 but no simple example designs except a complex example for which no link exists to download! How is that even possible? Is there a place that contains a lot of examples of application of CY7C67200 in its various forms starting from e.g how to implement it as a host of USB mouse and keyboard (what I need)?

In my case the CY7C67200 is connected to an external controller inside an FPGA on the DE2-115 board. Too bad the ISP1362 which has much information about how to use it from different places, became obsolete. Now I am stuck with CY7C67200 for which I do not find any example at all.

How is one supposed to get up and running with such a complex device without example designs?

Hello,

I want send any number of bytes from host PC to the endpoint of FX2LP in full speed mode.My doubts are:

1. How can I configure the endpoints or registers so that firmware gets to know about the written bytes.

2. After reading the TRM ,I understand that bmEPxEMPTY bit will be set after the packet size is reached.Can I set packet size,if yes,How?

3. I understand that Packet end can be used for IN transfer to send any number of bytes from FW.Can it be used for OUT bulk transfer also.if yes,How?

4. Can I use PF flag to acheive this..if yes,How?

Thanks In advance.An example will be of great help.

Hi,

  I use two chips CY7C68013A connect with one computer,there is a failure often occurs,one device of them often communication failure,must power off and restart.

  I can not find the reason of this problem,my board design or the driver program have some problem?

What should I do check this problem,look forward to your reply
Thanks a lot.

Hi,

Our company has a custom hardware that uses the CY7C64713-128AXC   how can I update the ezusb to cyusb3?  I am confused on what sdk i need i see EZ-USB FX3 Software Development Kit. I need some direction on how to get to the current cypress driver. 

After that is done would this allow me to use C# to development applications for my hardware? I see there is a .lib but i believe i have to migrate first from ezusb.sys to cyusb3.sys   

 I use visual studio pro 2015.   

thanks!

Dear all,

I two fundamental questions about architecture of EZ-USB FX2LP.

1. How many packets could be hold in a Quad Buffered Output Endpoint? (e.g. EP2).

- - This question arises while testing the Bulkloop example. The EP2 is configured as double buffered OUT. My first thought is that two consecutive "transfer data out" could be performed. But it turns out that 4 consecutive "transfer data out" could be performed before encountering error (code 997).

2. The RAM space for Endpoint 2, 4, 6, 8 Buffer is as large as 1024 bytes due to the TRM, then how is the quad buffered 512 bytes EP2 (or EP8) be implemented?

Please be so kind to share your knowledge. Thanks

where is the CY7C68013 driver for linux device? i cannot find it.

Looking forward to your prompt reply.

Hi all,

I am working on simple MPEGTS-USB converter using CY7C68013A and SiLabs demodulator. Currently I have implemented/working I2C proxy using EP1IN/OUT to configure demodulator, tuner etc. I have trouble with configuring Slave FIFO hardware with EP6 IN/BULK endpoint, there is no data from FIFO (timeout error from libusb library, no data while trying to read from kernel space). Could you please help me investigating what I am doing wrong?

I have checked that data from demodulator are provided to CY7C68013A using Saleae Logic analyzer. If you wish I could attach screenshot from the Logic app showing the communication between demod and CY7C68013A.

Please find the following HW configuration:

Please find the following HW configuration:  - CY7C68013A-56LFXC (56-pin QFN package)    * SLCS#     - pulled high, configured as normal PIO (PORTACFG = 0)    * PKTEND    - VCC    * FIFOADDR1 - VCC (EP6 FIFO)    * FIFOADDR0 - GND    * SLOE      - VCC    * SLRD/RDY0 - VCC   - demodulator (http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2169-D60-short.pdf)    * parallel data bus connected to PB[0:7]    * VALID pin connected to SLWR/RDY1 (active high)

Please find the following source code configuring CY7C68013A peripherals in TD_Init() function:

 // set the CPU clock to 48MHz  CPUCS = 0x10; SYNCDELAY;   // default to I2C bus freq = 400kHz  I2CTL |= bm400KHZ;   // Slave FIFO config, // External clock source  IFCONFIG = 0x03; SYNCDELAY;   // Disable FLAGD, SLCS pios  PORTACFG = 0x00; SYNCDELAY;   // FLAGD is configured as gpio, no signal from FIFO would be present on that pin  PINFLAGSAB = 0x00; SYNCDELAY;  PINFLAGSCD = 0x0E; SYNCDELAY; // FLAGC -> FF   // EP FIFO pin polarity (Active high SLWR (0x04))  FIFOPINPOLAR = 0x04; SYNCDELAY;   // Enable CPU features  REVCTL = 0x03;   // Order is important!  EP1OUTCFG = 0xA0; SYNCDELAY;  EP1INCFG  = 0xA0; SYNCDELAY;  EP6CFG    = 0xE0; SYNCDELAY; // BULK, IN, 512*4  EP2CFG   &= 0x7f; SYNCDELAY; // non valid  EP4CFG   &= 0x7f; SYNCDELAY; // non valid  EP8CFG   &= 0x7f; SYNCDELAY; // non valid   // The following code will restore FIFO default state (flags and bytes count)  FIFORESET = 0x80; SYNCDELAY; // set NAKALL bit to NAK all transfers from host  FIFORESET = 0x82; SYNCDELAY;  FIFORESET = 0x84; SYNCDELAY;  FIFORESET = 0x86; SYNCDELAY;  FIFORESET = 0x88; SYNCDELAY;  FIFORESET = 0x00; SYNCDELAY; // clear NAKALL bit to resume normal operation   // EP fifo config (WORDWIDE must be cleared on all FIFOs to switch PORTD to GPIO)  EP6FIFOCFG = 0x08; SYNCDELAY;// Auto IN, No zero length packets, 8bit wide  EP2FIFOCFG = 0; SYNCDELAY;  EP4FIFOCFG = 0; SYNCDELAY;  EP8FIFOCFG = 0; SYNCDELAY;   // out endpoints do not come up armed  EP1OUTBC = 0; SYNCDELAY; // arm the EP1 OUT endpoint by writing to the byte count   // Auto-commit 512-byte packets  EP6AUTOINLENH = 0x02; SYNCDELAY;  EP6AUTOINLENL = 0x00; SYNCDELAY;

Best regards,
 Jaroslaw Bielski

Hi,

I'm using FX3 dev kit and latest EZ USB FX3 SDK.
My device's bootloader got corrupted after flashing an image.
In CY Control Centre; the device is not being detected.
Even in the PC's Device Manager; it is not being detected.

Please help.
 

I am working at small device maker.

Where we are using the CY68013 to product .

Two devices that were shipped recently has been returned in failure.

I have received reports that D+/D- line is a short circuit. (shorted internally, not by board solder)

What is the cause of a short circuit?

Would there a way to protect on the circuit?

for past few years, problems did not occurred.