USB low-full-high speed peripherals Forum Discussions
hi, i want to program FX2LP's Ram in a C++ application.(precisely what Control Center do when click ProgramFX2=>RAM). but the function LoadExternalRam (in C# source of control center) is not available in CYAPI. what i should to Do?
thanks
Show LessI am in need of a a USB cable solution that would let me use an old CY3672B unit on USB. I assume the "USB" version of the programmer just used a USB->parallel adapter cable as I see signs of FTDI FTD2XX drivers in the software. Might there be a commonly available "USB printer" cable based on the FTDI chip that would work?
Alternately I can probably get by with an old version of the CY3672 programmer software that works with parallel ports on WinXP if I absolutely had to.
thanks,
Steve
hi.
when i copy fw project from c:\cypress\usb\target\fw\lp (all files in the folder) to an other location for example: ~my documents\keil_prg\lp and open the project with uvision3 it does not know the path for EZUSB.LIB and USBJmpTb.OBJ it looks in ~my documents\keil_prg\lib\lp for it .
also in another project when I write :
#include "fx2.h"
#include "fx2regs.h"
#include "syncdly.h"
after build this error occures : can't find file 'syncdly.h'
I checked for the file it was in the same folder as fx2.h and fx2regs.h in "c:\cypress\usb\target\Inc"
also unchecked Project -> 'Options for Target' -> the 'A51' tab -> and uncheck 'Define 8051 SFR Names'. according to :
http://www.keil.com/support/docs/1859.htm
could you please help me?
Show LessI bought a cypress CY7C68013A to restore the boot of a gigablue.
I tried it on Windows 10 x64 with Windows7 x32.
To use Broadcom interfacciarmi 3 study
The few times I can not connect after a few seconds I get the disconnection
with the following error: i2c removed
Can you help me ?
I thank you in advance.
Show LessHi all ,
We are using cy7c68013a with slave fifo to transfer data between FPGA and USB host . All seems
fine , we could send data by cyconsole correctly to FPGA . But we find something strange that if FPGA
do not fetch datas in SLAVE fifo quickly cy7c68013a would fail to transfer data again , at that moment
we must reset cy7c68013a chip to make it come back to work . EP2 is configured as Bulk-Out with 2x512-bytes
FIFOs . Here is the steps to reoccur this phenomenon .
1. Disable FPGA to fetch data from SLAVE FIFO
2. CyConsole sends 3 512-bytes packets to cy7c68013a , the 3rd packet would fail
3. Wait for some time . some seconds or some minutes .
4. Enable FPGA to fetch data again . SLAVE fifo would be cleared .
5. Try to send packets to cy7c68013a again .
6. Repeat 1 ~ 5 , cy7c68013a would suddenly fail to transfer data .
I read register EP2CS and EP2FIFOFLGS of cy7c68013a , EP2CS = 0x28 and EP2FIFOFLGS = 0x02 . FIFOREST could
not make EP2CS's value changed . EP0 still work fine at this time . It seems EP2 had entered wrong state .
Anyone knows what is wrong about cy7c68013a ? Thanks a lot !
Show LessHi,
I'm interested in evaluating the FX2LP18 USB controller in an upcoming low-power embedded design and I would like to purchase the CY3687 Developers Kit. However, according to the Cypress Website (http://www.cypress.com/documentation/development-kitsboards/cy3687-mobl-usb-fx2lp18-development-kit) this kit is out of stock and the only distributor that seems to carry this development kit (Avnet) also does not have it in stock.
Is the CY3687 Development Kit still available for purchase? If so, what is the current lead-time for this kit and where can it be purchased?
Is the MoBL-USB FX2LP18 controller still supported and recommended for new dessigns or would the FX2LP be a better choice for a low-power embedded design since the development kits for this part (CY3684) appears to be widely available from multiple distributors and directly from Cypress? Since this is a low-power design I would prefer the FX2LP18 since the core operates at 1.8 V vs. 3.3 V for the FX2LP.
As another possible alternative, since the new design will only be connecting to a USB 2.0 host, is it possible that the FX3 would consume less power than the FX2LP / FX2LP18 when connected to a USB 2.0 host?
Any feedback would be appreciated. I look forward to your response.
- Brad
Show LessHi,
I want to use this fx2lp CY7C68014A as a slave device for high speed data exchange at the rate more than 120mbps.
I want to know that at what rate the data is transferred on the Port B and port D of this IC when 48MHz crystal oscillator is provided.. I want to connect other peripherals on port B and D depending on the rate of data transfer.
Can any one help with this query..
Thanks,
Dhara
Show LessHi,
Our camera hardware is based on cy68013A usb2.0 controller. I am using CyAPI(1.3) to develop win10 camera software. We are using bulk transfer.
My transfer code transplanted from your bulkloop example. When I receive 1280 * 960 * 2 bytes from the hardware, the buffer in the hardware will always overflow resulting in I can't receive the frame data correctly. In this case, I'am using packetSize = 1024, packetNum = 1280 * 960 * 2 / 1024, transferQueueSize = 1 with the funcions BeginDataXfer/WaitForXfer/FinishDataXfer. However, if I increase transferQueueSize and decrease the packetNum, The data transfer will be more efficiently and in some values of the two, we will receive the data normally. Our speed is up to 35Mbytes/s.
So why do the different packetNum and transferQueueSize lead to different efficiency of receiving data? And what's the thing does BegingDataXfer/WaitForXfer/FinishDataXfer separately? The last question is where to reflect the transfer asynchronization.
Thank you.
Show LessI am trying to do a simple SPI based data logger and using cy7c65211 came with psoc4 kit in spi slave mode.
i am on windows10 and have written a simple c based application but its not working consistently. some time it works some times spi_read_write request fails with CY_ERROR_REQUEST_FAILED.
share your thoughts!
~SwK
Show Less