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Hi,
with the CY7C68013A one can change the clock speed by writing to the CPUCS register and choosing 12, 24 or 48 MHz.
After writing to this register, how instant is the speed change?
Like is there an internal PLL that has to lock to a new multilier factor first or something else?
Or does the chip after setting the register from 12 to 48 MHz immediately execute the following instructions 4 times faster?
Thanks!
Solved! Go to Solution.
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Hi,
Yes, the on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz, as required by the transceiver/PHY; internal counters divide it down for use as the 8051 clock. Once the CPUCS is written, the logic holds the request until all the clock inputs are at the same level. When at the same level, the logic proceeds to update the frequency and switch to a different clock domain. While doing so, however, the CPU clock is gated to make sure that latency in the clock switching logic doesn’t cause the old clock to glitch before switching over to the new frequency.
Regards,
Mallika
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Hi,
Yes, the on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz, as required by the transceiver/PHY; internal counters divide it down for use as the 8051 clock. Once the CPUCS is written, the logic holds the request until all the clock inputs are at the same level. When at the same level, the logic proceeds to update the frequency and switch to a different clock domain. While doing so, however, the CPU clock is gated to make sure that latency in the clock switching logic doesn’t cause the old clock to glitch before switching over to the new frequency.
Regards,
Mallika
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Hi Mallika,
Thank you for the prompt answer.
Can you tell me or is there a way to calculate the time it takes until the clock frequency is switched?
And by "gated", you mean that the CPU clock stops clocking until the switching is done? Would this affect the whole time from writing to the CPUCS register until the above time is over or will it only be gated during the very switching of the clock frequency?
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Hi,
There is latency involved in the clock switching logic but the exact value is not known.
Only when updating the frequency, the CPU clock is gated low so as to make the transition glitch-free.