HX2VL CY7C65542 : Detailed information on External Clock Input

[MiNe_85951]

Dear Sirs and Madams,

Please tell us the details of "Requirements for XIN (External Clock Input)".

AN72332 URL

https://www.cypress.com/file/122726/download

AN72332 --Guidelines on System Design using Cypress's USB 2.0 Hub (HX2VL), page 5 states:

Could you please provide us for the BW condition of this phase jitter?

For example, 12kHz to Nyquist frequency, etc.

Regarding this "External Clock Input Requirements",

Please let us know if there are detailed conditions such as masking by phase noise value.

Regards,

[Sananya_14 · Accepted solution]

Hello,

Currently we dont have the bandwidth values for the jitter RMS value mentioned in the App Note, we are checking internally on this.

Please refer to the KBA for the details on clock input requirements- Clock Jitter for EZ-USB® HX2LP™ and EZ-USB® HX2VL™ – KBA88959

Best Regards,

Sananya

[MiNe_85951]

Sananya-san,

Thank you for your reply.

Please check the conditions of the specifications.

We will wait for an answer.

Regards,

[Sananya_14]

Hello,

Unfortunately we currently dont have the clock specification conditions related data. However, we have run tests on our side with external clock on HX2VL and verified the jitter value mentioned in the App Note so kindly follow the same.

Best Regards,

Sananya