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USB Superspeed Peripherals

Anonymous
Not applicable

Dear Sir

   

I get a problem of my FX3 superspeed design, and it has  confused me for two weeks, so please help me.

   

In my design I use many_to_one DMA channel which has 2 valid socket and every socket has 4 valid buffers,my problem is everytime I start a new transfer I always lose  random data after 8buffers have transfered,beside this my data received is continuous.
I am sure that FPGA always sends data  a little later than PC receives data.

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2 Replies
Anonymous
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Hi,

   

I did not understand your problem clearly. Please help me in the same regard.

   

Following is your setup:

   

FPGA --> FX3 IN endpoint -->PC.

   

You have total 8 buffers in FX3 allocated for transferring data from FPGA to PC. Are you getting the right data when you are reading the first 8 buffers? Are you not receiving the right data after first 8 buffers?.

   

Please show me the data pattern logs, if possible.

   

Thanks,

   

Sai Krishna.

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Anonymous
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Hi Sai

   

Thank you for reply,and you get my point,I get the right data when I am reading the first 8 buffers and  I receive the right data after first 8 buffers,but between this two stage I lose data transfered from FPGA for about 1ms or more just like ProHerz encountered in http://www.cypress.com/?app=forum&id=167&rID=63294,

   

Thank you for help

   

 

   

Zhu

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