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The VSYNC of CMOS produce high pulse means a new frame is coming.Then when VSYNC is low and HSYNC is high,the data will be transmit.
But in the GPIF Designer, if the polarity of FV is high ,when FV is low,it means end of frame.
Should I set the polarity of FV active low in my designer?
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Hello ,
You can customize your GPIF II state machine.
As per your comments, the start of the frame is detected by the pulse in the VSYNC line. However, the VSYNC will go low within a short duration of time and will not stay high during the active portion of the frame.
Can you please let me know how can we identify the blanking period of the frame in your case?
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sorry,i amn't familiar with the CMOS ,its signal like this:
i think when the VSYNC is high is the blanking period
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Can you please share sensor datasheet?
What is value of VS_H? Is it configurable?
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the sensor is ov5642
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Hello Mini Nano,
--Please let me know, What is the time between VSYNC going high and HSYNC going high?
-We didn't find VS_H value in the data sheet.measure the VS_H value and share it.
Regards,
Anil Srinivas.