USB superspeed peripherals Forum Discussions

I have both the SX3 and FX3 kits here.  Since the SX3 doesn't allow any modification of the source code, I'm forced to use the FX3.  Clearly the Crosslink FPGA board that comes with the SX3 is pin compatable with the FX3, but is there any examples/code that would let me get started using it this way?   The FPGA examples from the SX3 kit are all compiled and as such, pretty much black boxes.   

Ultimately we'd like to use the Lattice Crosslink to our MIPI camera, and the FX3 to UVC.   Which this can ALMOST be done with the SX3, we also need to be able to send a SPI message on every frame, thus the need for a super trivial edit the code (but alas, they dont allow that).   I feel like I have all the parts here in front of me to do this but it's not clear how to put all the pieces together without some code/examples.

In short, is there any existing code for the FX3 that will communicate with the SX3 crosslink FPGA board.  Is the code for any of the SX3 fpga examples available?

• Hello cypress community,

I have attached my application without the sensor registers.

I would like to ask for help here. I am developing a driver for the omnivision sensor OV2311. It works with 1600x1301 resolution and 60 fps RAW 8 bits monochrome. 

I am using 16bit GPIF bus width, and the device has gated clock enabled.

I have an adapter board connected to the Denebola kit. THE ADAPTER BOARD IS GOOD, THIS IS NOT A HARDWARE ISSUE, THIS IS SOME BAD CONFIGURATION ON THE DMA/USB SIDE THAT I AM DOING WRONG. 

At the moment, I am able to establish video streaming successfully, but after some seconds I get CB Failure repeatedly and no frames any-longer.

CB failure

AplnStop:SMState = 0x7

AplnStrt:SMState = 0x1

CB failure

AplnStop:SMState = 0x7

AplnStrt:SMState = 0x1

Further, during valid transmission, I get a weird behavior with the producer and consumer DMA:

Prod = 56 Cons = 56 Prtl_Sz = 19904 Frm_Cnt = 4853 Frm_Sz = 2081600 B
Prod = 56 Cons = 55 Prtl_Sz = 19904 Frm_Cnt = 4854 Frm_Sz = 2081600 B

(as you can see above, sometimes the Consumer get 55 packets instead of 56 - WHAT DOES THAT MEAN?)

Finally, CyU3PMipicsiGetErrors always returns 0 in all types of errors in CyU3PMipicsiErrorCounts_t struct. Which confirms that the hardware is fine on the MIPI side in terms of signal integrity (Still, bad GPIF configuration could be the cause as well). This my GPIF configuration:

/* ov2311_RAW8_Resolution0 : */
CyU3PMipicsiCfg_t ov2311_RAW8_Resolution0 =
{
CY_U3P_CSI_DF_YUV422_8_2, /* CyU3PMipicsiDataFormat_t dataFormat */
2, /* uint8_t numDataLanes */
2, /* uint8_t pllPrd */
200, /* uint16_t pllFbd */
CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */
CY_U3P_CSI_PLL_CLK_DIV_8, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_8, /* CyU3PMipicsiPllClkDiv_t parClkDiv */
0, /* uint16_t mClkCtl */
CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */
1600, /* uint16_t hResolution */
0 /* uint16_t fifoDelay */
};

The host application has a python opencv-based script just grabbing the frames and calculating frame rate (very simple) connected through USB3.0 in a USB C connection to a Ubuntu 18.04 OS:

Hello guys,

                   I had gone through https://community.infineon.com/t5/Knowledge-Base-Articles/Streaming-RAW10-Format-Input-Data-to-16-24-bit-Output-Format-in-CX3-MIPI-CSI-2/ta-p/259142

                  I still can't realize why there is no difference in  descriptors and probe control structures  in packing of RAW 10 data into 16 bit or 24-bit parallel output?

Regards,

Nolan

We want use UVC firmware of FX3 transfer YUV422 images to host PC.We read AV75779 document and revise demo of cyfxuvc_an75779 .
We hope to complete the transfer of the following image parameters:
1) Image size: 1920 x 1080
2) fps: 25
3) color format: YUV422(the same of YUY2)
4) bits per pixel: 16
5) databus between of FPGA and FX3：16(DQ[15:0])
6) At present,we plan to test the fix graphics generated by FPGA, later we will use the sensor to output normal video stream.

I did the following modifications:
1) The modify of GPIF II Designer project
the width of FX3 Databus is 16-bits, I revise the GPIF II Designer project of FX3 UVC Demo. LD_ADDR_COUNT and LD_DATA_COUNT counters is 8183, creat new cyfxgpif2config.h, and copy it to the UVC_an75779 project.

2) The modify of cyfxuvcdscr.c
We updated the red part of Class specific Uncompressed VS format descriptor.
The other parts of cyfxuvcdscr.c have not been modified.
0x80, 0x07, /* Width in pixel 1920*/
0x38, 0x04, /* Height in pixel 1080*/
0x00,0x40,0x70,0x31, /* Min bit rate bits/s. 1920*1080*25*16*/
0x00,0x40,0x70,0x31, /* Max bit rate bits/s. 1920*1080*25*16*/
0x00,0x48,0x3F,0x00, /* Maximum video or still frame size in bytes(Deprecated) 1920*1080*2 */
0x80, 0x1A, 0x06, 0x00, /* 25fps */
0x01,
0x80, 0x1A, 0x06, 0x00,

3) The modify of uvc.c
We updated the red part of uint8_t glProbeCtrl[CY_FX_UVC_MAX_PROBE_SETTING].
The other parts of uvc.c have not been modified.
0x00, 0x00, /* bmHint : no hit */
0x01, /* Use 1st Video format index */
0x01, /* Use 1st Video frame index */
0x80, 0x1A, 0x06, 0x00, /* Desired frame interval in the unit of 100ns: 25 fps */
0x00, 0x00, /* Key frame rate in key frame/video frame units: only applicable
to video streaming with adjustable compression parameters */
0x00, 0x00, /* PFrame rate in PFrame / key frame units: only applicable to
video streaming with adjustable compression parameters */
0x00, 0x00, /* Compression quality control: only applicable to video streaming
with adjustable compression parameters */
0x00, 0x00, /* Window size for average bit rate: only applicable to video
streaming with adjustable compression parameters */
0x00, 0x00, /* Internal video streaming i/f latency in ms */
0x00, 0x48, 0x3F, 0x00, /* Max video frame size in bytes 1920*1080*2*/
0x00, 0x40, 0x00, 0x00, /* No. of bytes device can rx in single payload = 16 KB */
We did update io_cfg.isDQ32Bit ,it is CyTrue.it doesn’t seem to work in 16 bit databus mode.
/* Configure the IO matrix for the device. */
io_cfg.isDQ32Bit = CyTrue;

We did not get the fix image at the VirtualDub and VLC software of host PC, fps show 0.
We did not connect the serial port pin of FX3 at our FPGA board，so we could not get the debugging information of serial port.
We use the USB capturing tool to get some information. It seems that the video stream is transferred to de host PC but not been analyzed and displayed.
This is the screenshot at enclosure file.
We generate the YUV422 image data format is Y0 U0 Y1 V0 Y2 U2 Y3 V2
The value of Y fix 0x40, the value of U and V is fixed 0x80, so one fix gray image should be displayed.
The placement of Y is DQ[7:0]，the placement of U or V is DQ[15:0], each clock cycle FPGA send a YU or YV at the same time, is there any other additional setting?

Can you help us analyze why we failed to display the image?
thank you very much.

Greetings, Infineon Support Community !

My team and I are currently developing a custom FX3-based system, and we are experimenting some issues in programming our prototype with the Cypress EZ USB Suite SDK.

Trying to flash the FX3 component in I2C EEPROM mode with Control Center systematically fails, with the error message "Programming of I2C EEPROM Failed".

Having explored the support forums in search for answers, here is some additionnal information that might be relevant to figure out what's wrong :

- The custom device is connected to my PC with a USB3.0 to USB C cable.

- It does appear in Control Center, both as Cypress FX3 USB BootLoader Device  and as Cypress FX3 YSB BootProgrammer Device after clicking on Program > FX3 > I2C EEPROM . This should mean that the PMODE pins are correctly configured.

- In terms of hardware, the EEPROM on our PCB is the same as the one used on the CYUSB3KIT-003 (M24M02-DR), which makes me think that there is no need to change the bImageCTL bits of the bootable image file.

- We can actually flash our firmware in RAM, and it seems to work fine. That firmware was also tested on a CyUSB3KIT-003,for which we had no trouble in programming either in RAM or EEPROM.

- There are a few other I2C peripherals on our system, they are not active at system startup.

- Also, we unfortunately cannot access the UART for debug messages.

Programming the EEPROM is a necesary step in the development of our system, and we are running out of ideas for the debug.

Could anyone please suggest any reason why we might be encountering this issue, and how to solve it? 

Best regards,

Enzo

1. we use FX3 cypress  3014 chip;

2. we want to add cdc descriptor in CyFxUSBHSConfigDscr, so we want to know "uint8_t CyFxUSBHSConfigDscr[]" define, so how to find  documents?

tanks.

Hello, how can I  receive data from the FX3 without any streamer or collect data GUI on the host(PC) side using Visual Studio and save in a file or display on the console window and it should also be possible to add a way to measure the start and finish time to get the speed.

Thank you,

Sneha Dillikar

I am currently trying to test the firmware example cyfxusbspigpiomode provided, modified so it can have multiple slaves, but when i try to send some text with control center and visualize the MOSI signal with a logic analyzer, i jut see the same pattern everytime. 

i tried to modify the vendor comands supported, but there doesnt seem to be any issue with them.

I am looking for help getting around the FX3's limitation of the time taken when the FX3's internal DMA buffers are switched  following a full buffer or short packet. I am currently using the Slave FIFO example to stream UVC data to a USB host from an FPGA. The FPGA feeds 1080p data to the FX3 and when its 16KB buffer is full, it will take up to several microseconds for the new buffer to be set up so the FPGA can write again according to AN75779. During this time the FPGA cannot write to the FX3 but UVC data continues to come in to the FPGA. What is the best way to deal with this waiting period?

We are currently trying to incorporate a delay into the FPGA source which has a pause after the FPGA writes exactly 16KB worth of data to the FX3. However this is proving troublesome as if the FPGA doesn't write the exact correct amount of bytes as the FX3 will interpret it as a short packet and the FPGA and FX3 state machines will be wrong. Looking at AN75779, the issue is solved using multiple threads with the 'current' thread swapping as soon as a buffer is sent to the firmware, however we are already using the addressed version of the Slave FIFO example to send other data so we have no easy way to manually switch threads. Any help getting around this issue would be appreciated.