USB superspeed peripherals Forum Discussions
Hello!
I meet some problems about building the firmware example "USBVideoClass" in AN75779.zip,which is download from http://china.cypress.com/?rID=62824
I just down load it,then import it into EZ USB suite and build,without making any changes.
THe attchment show details of these problems.
THank you!
Show LessHello.
I design a USB system using FX3s chip. I need 32KB DMA buffer for USB control, and need more 32KB DMA buffer for SD card Control. but there are no allocated both memory. CyU3PDmaChannelCreate function returned a Error with number 16 meaned CY_U3P_ERROR_MEMORY_ERROR.
I think system has limit memory 32KB for DMA buffer.
according to default application memory map in cyfxtx.c, buffer area size is 224KB. Can I use whole buffer region for DMA buffer??
Thank you
Regards
Show LessHi,
I'm curently developping an application on the FX3 and I want to make a dynamic GPIF system. I mean, I wan't to program new waveforms without having to compile the application or have a fixed set of configurations, as we could do in the FX2LP.
Currently, I've looked at the GPIF registers, and I came accross a problem to populate the GPIF_FUNCTION registers. i've tried to find how are these transistions defined (the GPIF designer generate these values but I can't find how does it work. The FX3 TRM is quite light on this point as it states 'Truth table for transition function. Bit position X contains output when the 4 inputs constitute the value X in binary. For example, bit 2 = 1 means in3 = 0, in2 = 0, in1 = 1 and in0 = 0 will evaluate true for this function.' but it doesn't state were does inX comes from). I've tried to find a relation between a simple GPIF design and the transistion parameters but couldn't find it.
Can you please explain me how does it work.
Regards, Jerome
Show Lesshello, i develope slave_fifo 32 bit on CYUSB3014 and fpga xilinx kintex 7. i test stream_in.img, stream_out.img and loopback it is work good. good speed and no failure packets.
But when i rebuld project for stream_in_out or loopback and give new .img file i have failure packets. very rare, but still there, which is critical for our project.
what's the matter?
Show LessI updated the FW to 1.3.3 today and I am now getting the following errors. How do I fix this?
Building file: ../cyfxtx.c
Invoking: ARM Sourcery Windows GCC C Compiler
arm-none-eabi-gcc -D__CYU3P_TX__=1 -I"C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\\firmware\u3p_firmware\inc" -I"..\." -Os -Wall -Wa,-adhlns="cyfxtx.o.lst" -c -fmessage-length=0 -MMD -MP -MF"cyfxtx.d" -MT"cyfxtx.d" -mcpu=arm926ej-s -mthumb-interwork -o "cyfxtx.o" "../cyfxtx.c"
cygwin warning:
MS-DOS style path detected: C:\ccviews\klschult_GitTTC\tc_tools\SlaveFifoSyncMvrl\Release
Preferred POSIX equivalent is: /cygdrive/c/ccviews/klschult_GitTTC/tc_tools/SlaveFifoSyncMvrl/Release
CYGWIN environment variable option "nodosfilewarning" turns off this warning.
Consult the user's guide for more details about POSIX paths:
http://cygwin.com/cygwin-ug-net/using.html#using-pathnames
Finished building: ../cyfxtx.c
Building target: SlaveFifoSyncMrvl.elf
Invoking: ARM Sourcery Windows GCC C Linker
arm-none-eabi-gcc ./cyfx_gcc_startup.o ./cyfxslfifosyncMrvl.o ./cyfxslfifousbdscr.o ./cyfxtx.o -T"C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\/firmware/common/fx3.ld" -nostartfiles -Wl,-Map,SlaveFifoSyncMrvl.map -Wl,-d -Wl,--no-wchar-size-warning -Wl,--entry,CyU3PFirmwareEntry "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\\firmware\u3p_firmware\lib\fx3_release\cyfxapi.a" "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\\firmware\u3p_firmware\lib\fx3_release\cyu3lpp.a" "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\\firmware\u3p_firmware\lib\fx3_release\cyu3threadx.a" "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\ARM GCC\\arm-none-eabi\lib\libc.a" "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\ARM GCC\\lib\gcc\arm-none-eabi\4.8.1\libgcc.a" -mcpu=arm926ej-s -mthumb-interwork -o"SlaveFifoSyncMrvl.elf"
cygwin warning:
MS-DOS style path detected: C:\ccviews\klschult_GitTTC\tc_tools\SlaveFifoSyncMvrl\Release
Preferred POSIX equivalent is: /cygdrive/c/ccviews/klschult_GitTTC/tc_tools/SlaveFifoSyncMvrl/Release
CYGWIN environment variable option "nodosfilewarning" turns off this warning.
Consult the user's guide for more details about POSIX paths:
http://cygwin.com/cygwin-ug-net/using.html#using-pathnames
Finished building target: SlaveFifoSyncMrvl.elf
C:/Program Files (x86)/Cypress/EZ-USB FX3 SDK/1.3/ARM GCC/bin/cs-make --no-print-directory post-build
cygwin warning:
MS-DOS style path detected: C:\ccviews\klschult_GitTTC\tc_tools\SlaveFifoSyncMvrl\Release
Preferred POSIX equivalent is: /cygdrive/c/ccviews/klschult_GitTTC/tc_tools/SlaveFifoSyncMvrl/Release
CYGWIN environment variable option "nodosfilewarning" turns off this warning.
Consult the user's guide for more details about POSIX paths:
http://cygwin.com/cygwin-ug-net/using.html#using-pathnames
/usr/bin/sh: -c: line 0: syntax error near unexpected token `('
/usr/bin/sh: -c: line 0: `C:/Program Files (x86)/Cypress/EZ-USB FX3 SDK/1.3/ARM GCC/bin/cs-make --no-print-directory post-build'
cs-make: *** [SlaveFifoSyncMrvl.elf] Error 1
Show LessI just installed and am using version 1.3.3 to fix some USB3 Link error issues (I hope). However, this caused my code size to go beyond 128K to 142K. Are there a compile/linker switches that I can use to decrease the size?
Ken
Show LessHello
I test a simple Read/Write action using FX3S FPGA Dev Board.
I use a two SD cards. one is Class 10 another is UHS-1.
I test Read test a big file (about 1GB) , these cards are almost same performace.
In the Desktop PC. these cards performace difference is about 150%
(Class 10 card : 20 MB/s, UHS-1 : 33 MB/s)
I have some question.
Can I improve a performace on UHS-1 card ?
I set a 104MHz on SD CLK, but The CLK works 48MHz.
I change a CLK to 20Mhz, 26Mhz, 52Mhz, 104Mhz.
the CLK working 18Mhz, 24Mhz, 48Mhz, 48Mhz
Why 52MHz and 104Mhz are same CLK?
and can I improve a CLK over 48Mhz ?
Thank you
Regards.
Show LessHi, I was wondering there is a sample project for interfacing a basic image sensor with PCLK (external clk, coming from sensor), LV, FV, and 16-bit data width. The UVC example is overkill, I don't want UVC, but rather just reading the image data and transfer it via isochronous endpoint. I've been creating my own project looking at some of the sample projects as a reference, but I think I am missing something, probably simple. I need a project analogous to reading 16-bit ADC data, but strobing it with line valid and frame valid signals.
I've been "exploring" the FX3 with the superspeed explorer kit. Pretty sweet so far, but I can't for the life of me figure out how to get it to run in a raw packet mode. AKA I simply want a mode where it forwards link layer packets that don't have errors to RAM independent of their endpoints/etc.
Any hints if this is possible, or how to achieve it?
Of course I would like the opposite as well, a way to send a user defined packet back out on the superspeed bus.
Thanks,
Show Less