USB superspeed peripherals Forum Discussions
What could be the reasons that cause a 16kB burst bulk IN endpoint to NAK the request:
BulkInEndPt.XferData(buffer, 16kB)
I have 2 threads with four 16kB buffers each.
Show LessTo whom it may concern,
I am trying to use the CMP_DATA action in multiple states in a GPIF II state machine (for Cypress FX3 USB). However, whenever I set the "Comparator value" and "Unmask value" fields for one CMP_DATA action in the GPIF2 Designer, it appears to set the comparator and unmask values for all instances of the CMP_DATA action in the state machine. Is it not possible to use different comparator and unmask values in multiple instances of the CMP_DATA action (where each CMP_DATA action belongs to its own state)? For example, I would like to add the CMP_DATA action to State0 and set the comparator value to 128, while adding a CMP_DATA action to State1 and setting its comparator value to 64.
If it is possible, then the GPIF2 Designer's state machine editor would appear to have a bug. If that is indeed the case, then are the data structures in the generated header file documented (e.g. waveforms) such that it can be patched? As an aside, I am also interested in parallel to/from serial conversions using the state machine.
Thank you for your assistance. Sincerely,
Daniel Madill
Show LessWe are planning to develop custom board with cypress FX3 chip and FPGA. We are trying to implement FX3 synchronous slave fifo interface with FPGA.
1) In FX3 chip, what is the use of XTAL IN & OUT, CLKIN and CLKIN_32. It mentioned in document as “can be left unconnected if they are not used”. Anyways there is no “CLKOUT” pin in FX3 as FX2, so we can’t take outside to external FPGA.
2)In our design, we are using slave fifo interface and PCLK is driven form FPGA to FX3. Whether GPIF II slave fifo works on crystal clock or PCLK.? Also whether we can provide both clocks PCLK and Crystal clock to FX3.
Show LessHello
I find UART on S1-Port in FX3S but I can't find how to configure S1-port.
Could you tell me some advice?? I use custom board based on FS3S EVM. Only way to Communicate UART is S1 Port.
Regards
Shin.
Show LessHi,
I am building an application that would transfer data via SPI to a device connected on SPI. To start, I am trying to transfer data between host and CX3. I am using CyU3PDebugPrint to print data from CX3 to the hyperterminal. Is there a way I can transfer data from hypterterminal to CX3?
Also, I have to build the host application from scratch to talk to SPI slave. Are there any docs/tutorials that will be useful?
Thanks.
Show LessHow do I integrate the GPIF II Designer app into EZ-USB-Suite under Windows: there is a button (and menu item) for it in the IDE, but it's grey-ed out.
In preferences, there is a way to supply the GPIF II Designer path, but that appears to only be for Linux/MAC (apparently when the designer runs on a virtual machine).
~ Paul Claessen
Dear sir,
we are working with FX3 board.In that we use c# for application with CYusb.dll library.
we always get the device as NULL when using “CyUSBDevice MyDevice = usbDevices[0] as CyUSBDevice,If we not create single other endpoint (interrupt or bulk or iso).
we always get the device as not NULL(device is detected ) when using “CyUSBDevice MyDevice = usbDevices[0] as CyUSBDevice,If we create other one endpoint(interrupt or bulk or iso).
we want to access the device with out creating the other endpoints(interrupt or bulk or iso),is it possible or not.we want to transfer data only with controle endpoint.
please give your suggestion
I've read through AN65974 regarding the Synchronous Slave FIFO mode, and the associated FPGA example design. It seems like the examples cover the GPIF cases where there is a full DMA buffer transfer, then a partial or zero-length transfer. What about the case where the host is sending a partial packet to the FX3, like 128 bytes? Is it possible to notify the FPGA there is data to be read from the FX3? It seems like FlagC does not go high until the DMA buffer is completely full? Is that correct?
Thanks,
CYoung
Show LessI found that when I downloaded a new firmware to RAM by control center, there will be a vendor request 0xA0 sent to the firmware. If I process the request and return handled flag as true, the new device is recognized in control center with a delay of about 3s. But if I do not handle this request, the new device will be recognized immediately. Why?
Thanks,
Rover
Show Less