USB superspeed peripherals Forum Discussions
Dear Sir,
I know FX3/CX3 code can be download into internal RAM by control center tools and then re-enumerate again.
So, I also want to use this method in my application code. My application code find USB bootloader and then download CX3 firmware image into its internal RAM,just like what USB control center do. My app code will do two functionalities, one is USB CONTROL CENTER downloader, the other is a real application ,e.g. UVC host application.
Can you give me some advice for this case?
Best,
David
Show LessDear Sir,
I see the schematics of CX3 RDK, all DNU pins are connected with test pads, it is necessary to do that? or they can be float without any test pads connected?
Best,
David
Show LessHi there,
- The GIPF2 Designer project that comes with the AN has a suspicious-looking state called 'DSS_STATE' which seems to be an exact copy of the 'IDLE' state with exactly the same transition equations to other states. In addition to that, the transition equation that causes IDLE -> DSS_STATE also causes DSS_STATE -> IDLE. The related Designer project 'sync_slave_fifo_2bit.cyfx' from the 1.2.1 SDK does the same, whereas earlier versions didn't. What's the purpose of this DSS_STATE? Is it necessary (the 5-bit example doesn't have it) ?
- The documents describing the synchronous slave FIFO interface mention signal SLCS# all over the place but never clearly define if it is necessary at all: the state-machine works just the same if it is kept active (wired to low) all of the time (i.e. this signal may be removed from all transition equations without any behavioural changes), at no point is a SLCS# = 1 condition mentioned, and I can't find any explicit relation to FX3 hardware. My understanding is that I can get rid of this signal and may use GPIO[17] for other purposes (f.e. use it as an output pin). Is this true? I'm asking because I have to use 32bit sync slave FIFO with I2C and UART in our application and I am running out of GPIOs.
Thanks in advance for looking into this!
Ciao, Dani
Show LessHi,
I am running the synchronous slave FIFO firmware in 8 bit GPIF bus mode. I am using an FPGA to write data to the FX3. I am unable to get continuous data streams and the data miss is random. My implementation has two sockets corresponding to THREAD 0 and THREAD 1. My state diagram is described in capture.PNG
Can anyone help me in solving the issue?
Show LessHi all,
I'd like to know how to proceed to manage multiple configurations to have self/bus powered profiles.
I already modified the USB descriptors in order to have 2 configuration but is seems that CyU3PUsbSetDesc function only register the last one (as its description cryptically suggest...).
If the hw need to change configuration (eg. the external power is missing), do I have to use CyU3PConnectState to disable USB connection, register the new configuration with CyU3PUsbSetDesc, and enable USB connection again? (Re-enumeration)
In this case, should the USB descriptors explicitly declare 2 different configuration descriptor (Number of configurations = 2 into Standard Device Descriptor) ?
Thanks
Show LessThe FX3 cannot re-enumerate after download UVC firmware program from AN75779.zip.And I use 1.3.3 version of FX3 SDK .The SDK provide UVC example program also cannot re-enumerate after download UVC firmware program ,but other eaxmple program such as slavefifo can re-enumerate successfully.I do not know whether it's related to inf files.The control center can enumerate The FX3 bootloader device mode.
Show Lesswhen FX3 in reset, the GPIO will be pull-up or pull-down or high-Z? input or output?
Hello everyone
I am using slavefifo 2bit firmware. The PC program I use streamer.Now I want transfer data from FPGA through FX3 to PC. But I meet a problem .
When I write data to FX3 ceaselessly. Streamer will get no failures. But if I write data to FX3 everytime delay 40us for other device control, I will get a lot of failures at Streamer.
When I usb FX2, the same FPGA program will not get this kind of problem. What's wrong with my design. Is the waitforxfer() function using for speed synchronizing between the PC and the FPGA?
Show LessThe code I used is from AN65974 - Source files for FPGA code and FX3 firmware;
Hi,
I am trying to build an USB composite device (UVC + UAC + CDC). Among these, the UVC and CDC works. But the UAC is shown in Windows Device Manager with "This device cannot start. (Code 10)" error. I used Thesycon Descriptor dumper utility to inspect the descriptors. It reports error for the UAC Endpoint descriptor. I m confused with this.
I am using USB HighSpeed. Firmware is attached.
Show Less