USB superspeed peripherals Forum Discussions
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Continue to discuss the watermark issue Set DMA watermark of FX3 , the behaviour of "almost empty pin" (DMA_AEMP) is quite abnormal. This pin is configured as logic low in initial state. When slave and master are power up, DMA_AEMP outputs high. Until slave finishes to transmit data to master, DMA_AEMP outputs low.
When I break the connection between slave and master, and just power up the slave, DMA_AEMP outputs low. Please kindly advise.
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I hope to use 2 out endpoints and 2 in endpoints. I plan to use 1 dedicated flag and 1 dedicated partial flag for each out endpoint, 1 dedicated partial flag for each in endpoint. Therefore I need 6 endpoints in total. Is that feasible for FX3?
Show LessHi All,
I am having problems launching an OpenOCD session. I've followed the instructions configuring the session for my target interface, the CY7C65215, but when I try to open it, I get this error dialog:
Here's my setup:
Thanks for your help,
Scott
Show LessI'm working on UVC ISO with FX3, my code works fine in windows, but can not work in macos.
what's the difference between windows and macos of UVC driver ?
Do you guys have any idea about that ?
By the way , Is there any good debug tools on macos ? or any usbanalyzer like bushound ?
thanks a lot!
Show LessHi,
I have an FX3 which is as follows:
VIO1 is 1V8
VIO2 is 1V8
VIO3 is VADJ
VIO4 is 1V8
VIO5 is VADJ
AVDD is 1V2
VDD is 1V2
U3TXVDDQ is 1V2
U3RXVDDQ is 1V2
CVDDQ is 1V8
U3VSSQ is GND
VBATT is connected to VBUS
When VADJ is connected to 1V8, everything is hunky-dory. But when VADJ is connected to 2V5, my 1V8 rail for VIO1, VIO2, VIO4 and CVDDQ is shifted up to 2V6.
I don't have any conflict between 1V8 and 2V5 I/O. And the fact that is raised above 2V5 means it is most likely from the 5V or the internally generated 3V3.
Does my power rail combination not possible, they are normally between the limits express in the datasheet.
Any help is welcome. Thanks.
Etienne
Show Lessthe cyfx3s_msc firmware on a SFXS board supports cards of 512MB, 1GB, 2GB, 32GB in size; but doesn't support 4GB or 16GB.
Why ? I also have found no answer in the firmware itself. Any clue ?
Show LessI am working on fx3 development board. I used "USBVideoClass" example project to stream MJPEG hard coded video. But now i want to modify the same code to stream uncompressed yuy2 data. So please can any one suggest me that what all changes I need to do.
Show LessPreviously I develop firnware of FX2P. It has a conception of auto commit for an in endpoint. If the packet end signal does not asserted and data are continuously written into the in endpoint. The data would be auto commited. What is the meanning of commit. Does it mean the end of a packet. Does the similarity exists for FX3? I remmeber I should set the auto commit option for FX2L, but I have not seen the setting of auto commit for FX3.
Another question is: Does one packet have to exclusively occupy a buffer no matter how short the packet is?
Show LessHi
This is Herrick Oh at Ezsys in Korea.
My customer found CRC error problem in web camera that we supplied to them.
We used CX3 with bulk data transfer firmware (using CyU3PDmaMultiChannelCommitBuffer).
They checked it with Beagle USB 480 ( https://www.totalphase.com/products/data-center/) to check CRC.as the picture below
My customer's host is
1) Kernel : 3.4.39+
2) Android System : 4.4 kitkat
Did you see similar cases?
I hope to be informed how I can start to solve the issue.
Regards
Herrick Oh
Show LessI use slave fifo transfer of FX3. I use control center to send data to a out endpoint. FPGA connecting with FX3 does not read data from P port. The outcome is the host can send two packets to FX3 successfully and the third packet fails.
How to explain this?
Thank you.
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