USB superspeed peripherals Forum Discussions
Hi,
In CX3 UVC firmware, if I enable prints in Callbacks (i.e. Setupcb, uvcappdmacallback) firmware hangs in long run. Is there any way to overcome this?
Thanks in advance,
Vignesh Kumar R.
Show LessIn order to follow AN84868 instructions and use FPGA Configuration Utility to program the FPGA it is necessary first to power on the FX3 before powering on the FPGA.
Using my own code, I have seen that the PID changes if the FPGA was powered on before the FX3 device. So I tried to configure it nevertheless with that PID and with my own program. I do succeed on programming the FPGA but then I cannot send the bulk transfers. I think the FX3 never turns into slave fifo mode.
I do send it the B1 command, as I said, if I use my code with the FX3 device it works great when powering first the FX3.
The strangest thing is also that I printed UART messages in the following code snipet from cyfxslfifosync::CyFxSlFifoApplnUSBSetupCB():
Header 1 |
---|
if (bRequest == VND_CMD_SLAVESER_CFGSTAT) { CyU3PDebugPrint (4, "\r\tVND_CMD_SLAVESER_CFGSTAT\r\n", bRequest); if ((bReqType & 0x80) == 0x80) { glEp0Buffer [0]= glConfigDone; CyU3PUsbSendEP0Data (wLength, glEp0Buffer); /* Switch to slaveFIFO interface when FPGA is configured successfully*/ if (glConfigDone) { CyU3PDebugPrint (4, "\r\tSwitch to slaveFIFO interface.\r\n"); CyU3PEventSet(&glFxConfigFpgaAppEvent, CY_FX_CONFIGFPGAAPP_SW_TO_SLFIFO_EVENT, CYU3P_EVENT_OR); } isHandled = CyTrue; } } |
As I understand, this is the part that is called when recieving the B1 command in order to change to slave FIFO mode. As the documentation says:
"The FPGA Configuration Utility sends the vendor command 0xB1 (VND_CMD_SLAVESER_CFGSTAT) automatically after all the configuration data has been sent to FX3."
However, this messages ("\r\tVND_CMD_SLAVESER_CFGSTAT\r\n" and "\r\tSwitch to slaveFIFO interface.\r\n") are only printed with the case that is not working!
When it works this messages are not printed.
Some questions:
- Why does the PID changes if the FPGA was already powered on when I connect the FX3?
- Is it possible to fix this issue and make the programming work? I have a board that will have FX3 device integrated and both the FPGA and FX3 will be powered at the same time so I don't want to risk it not working.
Thank you.
Show LessThe UAC example in FX3 SDK reads audio data from the SPI flash.
I need to use the SlaveFIFO interface to input audio data to FX3.
Is there an FX3 example or project for UAC with SlaveFIFO?
Thanks!
Show LessOn the USB3.0 interface of the CY3014 (FX3), we see some deviations on the Spread Spectrum (SSC) 5GHz when comparing to the USB3.0 standard. The standard prescribes min.-5300ppm/-3700ppm and max.300ppm. USB PHY tests made at external digital testing lab, shows that the SCC is unstable and out of USB range (-5400ppm and 500ppm). We are using the recommended ASEMB-26.000MHZ-LY-T (10ppm) oscillator. What could be wrong? All other USB3.0 tests passes...
Show LessHello,
I have two FX3 chips in a JTAG chain connected to OpenOCD. I use FT2232H module and OpenOCD 0.10.0. Cypress SDK 1.3.4.
...\OpenOCD-20181130\bin>openocd -f myftdi.cfg -f board.cfg
Open On-Chip Debugger 0.10.0 (2018-11-30) [https://github.com/sysprogs/openocd]
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
trst_only separate trst_push_pull
jtag_ntrst_assert_width: 200
jtag_ntrst_delay: 200
RCLK - adaptive
adapter speed: 8000 kHz
fx3_1.cpu
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 8000 kHz
Info : JTAG tap: fx3_0.cpu tap/device found: 0x07926069 (mfg: 0x034 (Cypress), part: 0x7926, ver: 0x0)
Info : JTAG tap: fx3_1.cpu tap/device found: 0x07926069 (mfg: 0x034 (Cypress), part: 0x7926, ver: 0x0)
Info : Embedded ICE version 6
Info : fx3_0.cpu: hardware has 2 breakpoint/watchpoint units
Info : Embedded ICE version 6
Info : fx3_1.cpu: hardware has 2 breakpoint/watchpoint units
Info : Listening on port 3333 for gdb connections
Info : Listening on port 3334 for gdb connections
As you can see we have two ports 3333 and 3334 for gdb connection. I can debug first FX3 at 3333 port without any errors at all. But I can't access second FX3 at 3334.
OpenOCD hangs. I'm sure there is no signal integrity troubles at JTAG lines. Configuration files are attached.
Regards
Show LessHello everyone,
I am recently i am started working on FX3S writing data to SD card actually i am trying Sd card write from U to S port
when i tried debug with segger to check the steps the its showing ( Gdb version error ). while if debugged with slavefifosync example it is not why it is showing like that i am not getting after following the steps in Ezusb user guide also problem remains same .to over i added the source files from sd-card write programs to slavefifosync program and tried to build but in that its showing make file error and some undefined reference to following functions
1.CyU3PSibInit();
2.CyU3PSibRegisterCbk()
3.CyU3PSibSetIntfParams();
4.CyU3PSibStart();
i am totally struck at this point . i have attached that example if somebody helps me to sort out of this problem it will be very helpful .
thanks regards
Veerendra
Show LessHi, I'm trying to get the CX3 to work with a csi-2 bridge (toshiba TC358746AXBG). I'm starting with the ez-usb image sensor configuration tool and then i enter the bridge parameters.
Here are the parameter i measured on a scope.
And here are the result that i have. The state machine value is always 0x2 and i got no error from CyU3PMipicsiGetErrors(). I also used CyU3PMipicsiSetPhyTimeDelay(1,0x0B) to set a delay as suggested by the CX3 MIPI interface.
Does it need something else to work ? also, the value i measured on the scope. I also already tried to test if it work in continuous clock mode.
h-active = 30us
h-blank = 6.8 us
V-active = 24.8ms
v-blank = 8.48ms
Thank you for your help
Ps, when i edit some of the parameter ex. h-blank, hs-prepare... nothing change in h and c files. does the compiler directly use the cycx file ?
Show LessHi,
I got continued "CYU3P_PIB_ERR_THR1_RD_UNDERRUN" flag when wrote about 200K data to FPGA with below setting:
GPIF:32bit
DMA buffer size:16384
DMA count:4
host write 16384 every time
Could U help to explain this?
Show LessHi,
We are using FX3 chip and we have already gotten a certified driver with our own VID based on the modified cyusb3.inf. The device is recognized in windows and can be seen in Cypress control center. However, the Cypress sdk ifor C++ does not see the device. CCyUSBDevice->deviceCount always returns 0 unless we use Cypress's VID. What can be the issue? Thanks
(Urgent)
Show Less