USB superspeed peripherals Forum Discussions

We have the Patron Raid1 board we're demoing with and require some assistance from a software engineer with experience with the FX3S. We're really struggling with the [lack of] documentation and are struggling to get any of the test programs to function on the board.

Initial requirement is to assist with the modifications required for card-to-card transfers.

Anyone interested to discuss?

Best regards,

Josh

Hi,

  We have using the E-Consystem RDK and one converter board to connect our proprietary depth sensor and everything works well.

But if we try same firmware on our HW build, we cannot detect any frame, there is no error message on debug port. Only PCLK can be measured on PCLK_Test point.

Check the HW FAQ list that unused data lanes of CX3 must be connected to ground. But we have checked our HW build and RDK/converter board build, the unused data lane (D1/D2/D3) are all floating. Could someone give a suggestion what I can check for the no frame detect issue?

Thanks

Angus

   Is it possible to config the I2S pins as GPIO when FX3 GPIF is 32 bit?

   Thanks !

Hi Cypress,

I am working on the EZ-USB FX3 development. The FX3 works as a bridge between the PC and FPGA.

                                   GPIF

     PC > FX3 (slave) >>>>>> FPGA (master)

The GPIF interface used between FX3 and FPGA is based on AN87216. The problem that I am facing is during the SLAVE_RD. According to the application note, the valid data always appears after 2 cycles while the SLRD is low. From the capture below, CLK[221] and SLRD = 0, the valid data should be appeared at CLK[223]. However, the valid data [001F] appeared at CLK[224].

This above case always happens when the SLRD goes from low to high. Any idea?

** I forgot to mention that the watermark is 2.

     CyU3PGpifSocketConfigure(1, CY_U3P_PIB_SOCKET_1, 2, CyFalse, 1);

And, I read the application note AN65974 section 8.3. Did it mean the #SLRD should keep asserted for one more clock cycle (2 x (32/16) - 3) for the data 001f?

Thanks!

Jason

Hi,

I would like to create a CX3 project with library output (similar with E-Consystem libCX3OV5640.a) to protect some proprietary setting of this project before sharing the project to co-work(sensor maker) company. Is any document to describe this?

Thanks

Angus

Hi sir,

Is there any sample code available for generating MCLK freq to a sensor?

i understood that MCLK just for test, and will not use that for mass production.

thank you

Hi,

For identifying the firmware version i had earlier posted a ticket, Identifying the version of firmware in CX3 UVC-CDC device

I had solved it in a different way by adding the revision into the UVC descriptors.( device release number in the Standard device descriptor).

Now i also need to add the firmware build date along with this information.

Is there an option to add it into the UVC descriptor ?

If not what are the other ways to achieve the same.

Another question would be in the ticket Identifying the version of firmware in CX3 UVC-CDC device​,It describes using vendor commands. How can i initiate a custom vendor command.( Python would be the preferred language)

Regards

Ajay

HI,

A note on page 8 of the CYUSB306X datasheet states the following:

REFCLK and CLKIN must have either separate clock inputs or if the same source is used, the clock must be passed through a buffer with two outputs and then connected to the clock pins.

For the same source approach, I presume the buffer is required to optimize signal integrity. However, what if I were to route the output of the clock source (i.e. oscillator) to REFCLK and CLKIN in a daisy-chain fashion with a termination resistor to GND at the end of the trace as shown in the figure below? Note that the termination resistor matches the characteristic impedance of the trace to ensure no reflections. Assuming that the clock source has a very low output impedance, it seems that the resulting waveform at the REFCLK and CLKIN inputs would meet the requirements of the CYUSB306X. In other words, is there some other reason - aside from signal quality degradation - that the buffer is required if a single clock source is used for REFCLK and CLKIN?

Regards,

James

Hello,

Question to the State Machine from the GPIF II Designer.

is there a possibility to switch a state after a spezified time?. Something like, if you in State1 longer then 5 Seconds, goto state 2

kind regards
Matthias Macho