USB superspeed peripherals Forum Discussions

Hello,

We want to development 4K@30fps camera and survey CX3/FX3 now. But some points let me confuse.

1. We have contact three CMOS module maker (SONY/Socionext/Thine) to discuss using CX3  structure. They think the CX3 throughput only 1.6G~2Gbps. But we have test FX3, then it can meet it.

2. The CX3 can provide 4K@30fps? or FX3?

3. CX3/FX3 can support YUY2 format?

MCU and FX3S are connected via the SRAM interface as shown below.

I use the GpiftoStorage example code provided by Cypress.

HOST PROCESSOR can not connected eMMC memory through FX3S.

Is the HOST PROCESSOR unable to connect the eMMC memory by Method Async SRAM interface.?

Help me. If you know how to solve this problem, please help me.

The FX3S example code alone is not sufficient to resolve this issue.

CY-U3P-PIB_SOCKET_0 is 0x0100,  CY_U3P_SIB_SOCKET_0 is 0x0200.

How write  form HOST PROCESSOR to FX3S GPIF?

Hi, I am using the EZ-USB FX3 Kit to get data from an FPGA to a host computer through GPIF II.

The design on the FPGA is pretty simple, the handshaking between the FX3 kit and the FPGA achieved by only two control signals: RESET and WRITE_ENABLE, and the PCLK signal as clock source for the FPGA at 80 MHz.

The data transfer rate is only 40 MB/S.

The firmware on the FX3 Kit is "GPIF_Example2.img" from the downloadable examples related to "SupperSpeed Device by Example" book, and on the host computer I use the "CollectData.exe" program which also come with the book's examples.

"CollectData" triggers the RESET signal and start the state-machine on the FPGA, the FPGA's design then asserts eventually the WRITE_ENABLE signal once every 8 clocks to trigger the state-machine of the GPIF II to save the 32 bit value into a DMA buffer and send it to the host computer, and that what the first example should do if I understood the example!

The problem is as flowing:

case 1 : When I upload the firmware into the FX3 kit and run the "CollectData" application to Start Data Transfer, the application receives 1048576 bytes of unknown data of value of "0xEF" then ‭‭16384‬ bytes of correct data from the FPGA is received followed by another 1032192‬ bytes of value of "0xEF" , and repeatedly the application receive the same data pattern (1048576 bytes of value of 0xEF and 16384‬ bytes of correct data, 1032192‬ bytes of value of "0xEF").

case 2 : In every attempt to Start Data Transfer again, the "CollectData" application receive only that strange value of "0xEF" !!!

only when I reset the FX3 Kit and upload the firmware again I got the same result as in case 1.

I used a logic analyzer to make sure that the FPGA design works correctly so please advice me what can I do to make the firmware works correctly every time, and to get correct data, not that dummy "0xEF" ?

Thank you in advance for any help.

Regards

I am using SuperSpeed explore kit for debugging SPI port. The SPI port on J7 interfaces a SPI flash memory.  UART at pin 48 and pin 49 is used as debugging port. I tried to read back 256 bytes from flash memory starting at page address 1000 and display values to UART port. Firmware is revised based on example code UsbSpiRegMode. I found that the process is stuck at the reading status register. It is not able command the write enable properly. The RDSR value would be 0x00 all the time. The MISO is always low observed by Oscilloscope.

To confirm the hardware, firmware image is downloaded to SPI memory when FX3 is configured to USB boot mode. FX3 can boot properly from SPI memory it is configured to boot from SPI. But one thing I can't understand, I was not able to detect any signal on MISO at power on booting from SPI.

Code is attached.

Thanks in advance for any help.

Hi All,

We are facing an issue with reading the data from SPI Flash using CX3.

SPI Flash Part Number - SST25PF040C (Microchip)

Please find the issue description below.,

Description :

On long-term usage, somehow the BPL bit in status Register of SPI Flash has changed to '1' and after that the Cypress Bootloader fails to read the Data from SPI Flash. To recreate this issue, we are manually setting the BPL bit to '1'.  

When the BPL bit of SPI flash is set to '1', the bootloader Firmware in CX3 Chip fails to read the data in SPI Flash and falls back to "Cypress FX3 USB Bootloader Device". 

Our Findings :

1. A Firmware to read the whole 512KB in SPI Flash is flashed in RAM.
   1. In this case, Read is successful and we can find that valid Firmware is present in SPI Flash.
2. Using the Second stage Bootloader Firmware available in "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\boot_fw\src".
   1. In this firmware, the SPI _BOOT macro was defined to boot from SPI Flash.
   2. The Firmware can successfully transfer the data from SPI flash to RAM and can boot as a video device.

From the above findings, we can conclude that,

1. On changing the BPL bit to '1', read works Fine. But only the Cypress Bootloader Firmware present in the chip is unable to read the data from SPI Flash.
   

Questions :

1. Why the Bootloader Firmware present within the Chip is unable to boot from SPI Flash?
   
2. Can anyone help me with finding actual source code of Bootloader firmware present in the CX3 chip?
3. Why setting the BPL bit to '1' affects the Bootloader firmware to Read the data from SPI Flash? Whats the Difference in setting the BPL bit to '1' or '0'? 

I see on the product roadmap that there is a USB Controller coming that will support 3.1 Gen2( 10Gb/s ).  I’m unable to find any additional information regarding the product though. Can you tell me when that product is expected to be released?  Will there be a controller that supports USB 3.2?

Hi,

     I use FX3 with the sensor IMX316, the resolution is 480*182 @ 30fps, raw12. The mipi clock is 200MHz

1. I can't get the correct datas. I add log, shows below. The CyU3PDmaMultiChannelGetBuffer get data error. It is confirm that the sensor can output datas correctly (I measure the MIPI signal, it is correct).

CyCx3AppStart 863

AplnStrt:CyCx3AppStart

AplnStrt:SMState = 0x2

CyU3PDmaMultiChannelGetBuffer failed status = 0x0

CyU3PDmaMultiChannelGetBuffer failed status = 0x0

CyU3PDmaMultiChannelGetBuffer failed status = 0x0

CyU3PDmaMultiChannelGetBuffer failed status = 0x0

CyU3PDmaMultiChannelGetBuffer failed status = 0x0

2. But i catch the package, it seems that PC can get some disorderly datas.

3. The configuration is as below:

Is there someone who can  give some suggestions? How to debug it?

Hello,

We want to use CYUSB3025 part as a mass storage device which uses eMMC memory. For that, I was referring to FX3S DVK, and FX3SMassStorage example given in the SDK and it works well.

I tried running the same code for CYUSB3025(SD3) chip but it is not working. I would like to know if there's any changes I needed to make in the code? How do I change the part number in the SDK? Is there any API available that I can use for that?

I would really appreciate any possible help with this.

Thank you very much in advance,

Kishan Patel

請教一個關於AN75779 - UVC example裡state machine的問題:

在PUSH_DATA_SCK0指向PUSH_DATA_SCK1的路徑上，

為了保險起見，我希望在切換到thread1前，先確定thread1是否已可使用(包含確認Descriptor是否已經載入完成等...)，

因此嘗試加了一個trigger "DMA_RDY_TH1"，如下圖所示

但卻收到錯誤訊息:

Trigger variable ‘DMA_RDY_TH1’ cannot be used in transition equation between states ‘PUSH_DATA_SCK0’ and ‘PUSH_DATA_SCK1’.

‘Thread number’ of Action ‘IN_DATA’ need to be ’Thread1’ for using trigger variable ‘DMA_RDY_TH1’

我想在Thread1上使用IN_DATA來取樣資料，但卻不能先確認thread1是否已可使用? 不知是不是我誤解了trigger "DMA_RDY_TH1"的意思了@@?

1. ps. 同樣的概念，測試過在WAIT_FULL_SCK0到PUSH_DATA_SCK1的路徑上多加一個trigger "DMA_RDY_TH1"就不會有錯誤訊息並可順利編譯...

謝謝!

ref: AN75779 example https://www.cypress.com/documentation/application-notes/an75779-how-implement-image-sensor-interface-using-ez-usb-fx3-usb