USB superspeed peripherals Forum Discussions
Can use device be configured to be super speed only?
If so, what to do - remove CyU3PUsbSetDesc for device descriptors and configuration descriptors in CyFxBulkLpApplnInit?
If not, does USB support null configuration with zero interface? Or null interface with zero endpoint?
Show LessI am trying to develop a UWP windows application with the Cypress FX3 and started with the FX3 development kit. The attached code is working in my WPF application, but in UWP it doesn't work. The code i do have from the Cypress examples. So i want to use the CyUSB.dll in my UWP application.
In the appxmanifest i added the details shown in the device manager. How i can get it to work?
Thank you for any help!
Show LessIn AN87216 slave firmware, there is
CyU3PGpifRegisterCallback(CyFxApplnGPIFEventCB);
CyU3PDmaChannelSetWrapUp(&glChHandleSlaveCh1);
What is the purpose, is this required as a work around for chip bug?
Show LessHello
They want to add I2S Mic to their USB camera. But, Based on the CX3 documentation, I2S is a master and a transmitter.
Is there any wat CX3 operate as I2S Slave function? Or is it possible to use it
What can I do if I want to receive Mic's I2S? Or it is possible using SPI or GPIO?
Best Regards
Arai
Show LessHello,
I am transferring video data from FPGA to FX3 S0 port(SD Card) and able to receive it succesfully. When I am seeing video using host application(GUI),the data is receiving very slow i.e.. only one frame for 10 seconds.How to increase the data transfer rate?
Regards,
Srujana.
Show LessHi All,
I am trying to interface the Sony IMX327 sensor with the CX3 and have run into problems configuring the CX3 using the MIPI Receiver configuration tool.
The sensor's specs are 1080p (1920x1080), RAW10 @ 60fps. The vertical retrace is 6 lines and horizontal retrace is 20 pixels. When I enter these parameters, the receiver configuration shows the Output Pixel Clock min and max values are inverted, that is min shows 125.11 MHz and max shows 100 MHz. Of course no set of values prevents showing an error for this field. Only if I reduce the frame rate does the inversion disappear. As I understand it is not possible to reduce the sensor's output rate. I realize that the output pixel clock isn't actually used, at least in our system, but believe it is signaling some underlying problem.
Thanks for your help.
Scott
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I would like to build my own board that attaches to the FX3 Development Kit board. I need a mechanical drawing of the FX3 board (preferably in PDF Format) that shows the spacing between the connectors. Is such drawing available?
Thanks,
Mo
Show LessI use the sample code "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\dma_examples\cyfxbulklpmandcache", I use API CyU3PDeviceReset(CyFalse); to reboot device, The function CyFxBulkLpApplnInit() will be invoke after execute "CyU3PDeviceReset(CyFalse)", when plug in USB device, the function CyFxBulkLpApplnInit() will be invoke too, so the function CyFxBulkLpApplnInit() will be invoke two times(the first is plug in usb device, second is to run CyU3PDeviceReset(CyFalse) ), I want to identify which time to execute CyFxBulkLpApplnInit(). example: when hot plug USB device on host, do action A inside function CyFxBulkLpApplnInit(), after execute CyU3PDeviceReset(CyFalse), then run CyFxBulkLpApplnInit() again, do action B(Not do action A) inside function CyFxBulkLpApplnInit(). how to implement it?
Show LessSorry about the late response, now the old post can not be replied.
What about a new solution: remove 5V jumper J3 for both CYUSB3KIT-003, and wire out from both board's J3-pin2 and GND and connect to one common external 5V power source. And cut pins as described by "001-87216_AN87216_Designing_a_GPIF_II_Master_Interface.pdf". Then no problem can happen anymore, both board are supplied by the same power source at the same time. This give another benefit - easy to power cycle the two board at the same time.
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hi,各位
问题描述如下:
1、 采用同步slave 的方式进行数据的读写;
2、 FPGA的波形如下图,当flaga与flagb同时有效时发送累计数到上位机,但是上位机接收的数据是错乱的;请帮助看下原因
3、 原厂固件的测试数据截图如下图,数据错乱无法分析;
4、 自己按照网上修改的固件,(32bit,1k的深度),数据奇数被偶数给替换。
FPGA波形:
原厂固件数据截图:
自己修改的固件截图:
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