USB superspeed peripherals Forum Discussions
Hello,
I download my UVC firmware to RAM with control center, and preview the images with "WebcamViewer".
I encounter one problem, that is the device reset to "Cypress USB BootLoader" device after grabbing several frames and UVC device is gone.
May I ask for the help to solve this issue, is it a hardware issue or software issue?
Thanks.
Show LessHi,
We use FX3 USB3 Explorer Kit to simulate USB camera (USBIsoSourceSink project), in a real USB web cam, we able to see flickering pictures when the time_service_interval > 125us (according to the USB3 spec, the time interval between ITP packets should be 125us).
we trying to reproduce the flickering issues with the FX3 device and we are using the streamer app form the SDK, failure counter keep be 0.
We saw in the FinishXfer function that the fail criteria\error is depend on USBDstatus, NtStatus and the result of the function GetOverLappedResult() function,
there is any way to give us indication to detect that the time_service_interval > 125us?
if no, is there any way to detect that the time_service_interval > 125us?
thank you and have a nice day,
A.K
Show LessHi,
We are working with the CX3 component as a UVC class with an OV5640 camera sensor and we are also developing windows host application for the same. We need support on how to get a still image from the camera sensor by use of UVC still image trigger command. Currently, we are able to capture still image from video stream by use of the "IMFCaptureEngine" of windows media foundation but we need to do it using UVC still image trigger command. Can anyone please point our some reference source or documentation for the same?
Show LessHello
Normally, when writing FW and booting, I think that Dip-switch will be used to switch PMODE. At the customer's request, the PMODE setting is "fixed" without using Dip-switch.
Q) Is there a way to write FW from the HOST (Control Center) to SPI Flash and then boot from SPI Flash? Please let me know if there is a method in which PMODE is fixed and both(USB and SPI) boot options can be set.
Best Regards
Arai
Show LessI ported the AN65974\FPGA Source files\fx3_slaveFIFO2b_altera\fpga_streamIN design to an Altera EP3C5 board that my Superspeed Explorer card mounts to.
Using the sync_slave_fifo_2bit.cyfx example GPIF state machine with the cyfxslfifosync example firmware and my FPGA-generated PCLK of 80MHz, the set up works
fine with USBControlCenter.
But I have some DAQ in my eventual application that wants to lollygag along at 40MHz. Reprogramming the 3C5 for 40MHz PCLK, I am unable to find a combination of clockConfig.mmioClkDiv, pibClock.clkdiv, gpifclkdiv, clockConfig.dmaClkDiv, and clockConfig.cpuClkDiv that works with the example firmware&GPIF setup. In some instances the logic analyzer captures a "runt" frame on the FIFO interface on download of the firmware followed by ...nothing. In other cases, the interface is simply dead
(Always using USBControlCenter data transfers to tickle the FX3).
What method is there to successfully using a lower speed clock on the FX3 Explorer sync slave FIFO interface?
Show LessHi,
I am facing an issue while reading the register of the OV5640 Camera sensor (I2C slave device in my setup) from firmware with "CyU3PI2cReceiveBytes" API through I2C. However, The camera module is working fine as I am able to stream it from Windows Host.
CyU3PI2cReceiveBytes returns CY_U3P_ERROR_FAILURE. I have further debugged the issue with "CyU3PI2cGetErrorCode" and it returns CY_U3P_I2C_ERROR_NAK_BYTE_0. Please find the code snippet below,
preamble.buffer[1] = 0x30;
preamble.buffer[2] = 0x2A;
preamble.buffer[3] = devAddr | 0x01 ;
preamble.ctrlMask = 0x0004;status = CyU3PI2cReceiveBytes (&preamble, buffer, 1, 0);
CyU3PThreadSleep(1);
if (status != CY_U3P_SUCCESS)
{
CyU3PI2cGetErrorCode(&errorCode);
return errorCode;
Hi Cypress Support,
We are refer to Asyn Slave fifo AN65974 , to use two DMA Thread to transfer data with FPGA then forward the data to USB.
But after some time, I see CyU3PDmaMultiChannelCommitBuffer(...) get error code (0x47) = CY_U3P_ERROR_INVALID_SEQUENC.
Then The FPGA still check the status of FLAGA and FLAGB is Low.
I also attach the GPIF design file and my application code.
What's the reason lead to the issues?
Thanks,
Martin
Show LessHello support,
I try to add "CyU3PDebugPrint (4, "CyU3PDmaChannelGetBuffer buf_p.size %d\n", buf_p.size);" into CyFxBulkSrcSinkDmaCallback (cyfxbulksrcsink.c line 227).
then streamer tools can not get data from IN endpoint.
By My understand, it maybe get very slow transfer data speed.
Can you let me know what is reason on the issues?
for your reference, I also attach my modified code on the offical sample code USBBulkSourceSink.
Thanks,
Martin
Show Less