USB superspeed peripherals Forum Discussions

Hello.

I have a Question about VSYNC_test signal of CX3.

When the MIPI signal is valid data, the VSYNC_test signal is output correctly.

However, when the MIPI signal stops, so does the  VSYNC_test signal.

If MIPI signal stops in the middle of the frame, it will be high level.

If MIPI signal stops  during V blanking, it will be low level.

Is it possible to set the  VSYNC_test signal output to Low level even when the MIPI signal is stopped in the middle of the frame?

Hello. I am Lee.

I use 16bit Data Bus GPIF at FX3 chip and FX3 is connected W25Q32JV as spi boot loader memory.

I want to save or load user data without touching the boot image area.

1. How do I check the boot image size in cypress EZ USB suite ?

Then, is there any problem with using parts other than that size area?

2.

Can I use this example?

https://korea.cypress.com/documentation/code-examples/ez-usb-fx3-usb-spi-dma-mode-example

3. Is there any problem if I receive'output.image' through communication after booting USB and write it back to the boot area?

Wait for your answer.

thank you.

Hi. cypress

when FX3 CYPUSB3014 use 2 bit socket, the UVC is ok,and configurate 4bit is error, detailed information is attachment file, 请给些建议，谢谢！

Dear fellow engineers!

I would like to communicate from the FX3 GPIF II bus (master) to an Intel FPGA with Avalon-ST slave which includes backpressure (ready). As far as I understand the GPIF II interface and associated state machine designer, it is possible to include a input signal (CTRL) into the state machine and use that as condition to move between states, but there is a limitation on the minimum number of data words that is transerred each state with DR_DATA (1024 bytes to be presice).

The Avalon-ST bus requires that the backpressure signal (ready) to be monitored and the host (the FX3 in this case) must drive no more than six data words after the deassertion of the backpressure signal (ready). This means that the GPIF state machine should evaluate the input signal (CTRL) on almost every cycle it wants to write data, instead on every N words. With other words, DR_DATA should write no more than 6 words each time.

My question comes down to: Can the GPIF state machine evaluate an input signal (CTRL) on (almost) every cycle?

Or, another way of looking at it: Can the number of words writen with DR_DATA be lowered, to let's say 4 ?

Background info: I would like to use the FX3 GPIF bus to configure a Stratix 10 FPGA , which exposes a Avalon-ST interface (8, 16 or 32 bit wide). By using BULK transfers from the host PC to the FX3, we would like to configure the FPGA at max GPIF clock freq (approx 100MHz.) to avoid needing the FPGA to load it's image from onboard FLASH.

Thank you in advance for your help, it's appricated!

Best regards,

Gerben

Hello,

I am currently working with Development Kit Denebola.  this hardware has two memory types to store the firmware (I2C EEPROM and SPI FLASH) and I can store it in both without any problem. However I am carrying out an application which needs to work with the SPI Flash memory, I mean, I need to write and to read values from the memory.

For this reason, i have the following questions:

- Is there any API focused on to communicate with the FLASH memory? In case yes, Where could I find it?.

- Which functions from this API are able to write the memory and to read from her? Could you give me some example of use?

Thanks!.

Hello sir/madam,

I am using CYUSB301X/CYUSB201X controller for USB 3.0 communication for specific application.Now I want to use Ethernet communication in same board. is it possible without changing the CYUSB301X/CYUSB201X controller?

I came across your CYUSB3610 Gigabit Ethernet Bridge Controller. Can i use it in above application as add on board?

Thanks

Hi,

I am planning to use FX3 to convert UVC USB3 packets to native Video (YUV 422) format. Is it possible to use FX3 for this application?

If yes, Does anybody have any reference design to start with?

With Regards,

Bhat

       我们目前在用3065+ov5640做一个摄像头，也是想用UVC，但是编出来还是有问题，请问你们有没有OV5640的uvc可用固件，

我们想验证一下这个板子是否可以正常工作。谢谢！

Hello,

We developed a custom camera and created a CX3 project using the Eclipse project wizard. This is a custom raw data bulk streaming project and is not a UVC project. Watching the USB transactions with a USB protocol analyzer, we never see EP3 bursting. All the transactions deliver a data payload of 1024 bytes only.

Below are snippets of the CX3's channel create function, and the USB descriptor for bursting (I have replaced the manifest constants with the actual values):

dmaCfg.size = 0x8000;

dmaCfg.count = 3;

status = CyU3PDmaMultiChannelCreate (&glChHandleUVCStream, CY_U3P_DMA_TYPE_MANUAL_MANY_TO_ONE , &dmaCfg);

// Super Speed Endpoint Companion Descriptor

0x06,                                                       // Descriptor size

CY_U3P_SS_EP_COMPN_DESCR,     // SS Endpoint Companion Descriptor Type

0x0F,                                               // Max number of packets per burst: 16

0x00,                                                       // Attribute: Streams not defined

0x00,                                                       // No meaning for bulk

0x00

As a reference, we have a FX3 product that we tested on the exact same USB port. With our FX3 product we see bursts of 16KB for the data payload. The FX3 DMA configuration is the same as the CX3 except that the FX3 is a one-to-one socket DMA channel, and it's also setup as CY_U3P_DMA_TYPE_AUTO.

Questions:

1. What would prevent the CX3 transactions from bursting over USB?

Thank you.

Hello

I'm Juyeol.

I plan to make the FPGA Configuration using GPIF master mode.
I have a question during fw coding, so please contact us.
Currently, I am using only the output value after deleting the input from the GPIF designer tool that has been uploaded(AN87216 Master mode).
Control Center provided by cypress, there are Control Endpoint and Bulk Out Endpoint. When I take an oscilloscope, data goes out from the Bulk Out Endpoint but not from the Control Endpoint, but I wonder if the two are different.

I think settings are same..

Thanks.

        if ((bTarget == CY_U3P_USB_TARGET_ENDPT) && (bRequest == CY_U3P_USB_SC_CLEAR_FEATURE)

                && (wValue == CY_U3P_USBX_FS_EP_HALT))

        {

            if ((wIndex == CY_FX_EP_PRODUCER) || (wIndex == CY_FX_EP_CONSUMER))

            {

                if (glIsApplnActive)

                {

                    CyU3PDmaChannelReset (&glChHandleBulkLpUtoP);

                    CyU3PUsbFlushEp(CY_FX_EP_PRODUCER);

                    CyU3PUsbFlushEp(CY_FX_EP_CONSUMER);

                    CyU3PUsbResetEp (CY_FX_EP_PRODUCER);

                    CyU3PUsbResetEp (CY_FX_EP_CONSUMER);

                    CyU3PDmaChannelSetXfer (&glChHandleBulkLpUtoP, CY_FX_DMA_TX_SIZE);

                    CyU3PUsbStall (wIndex, CyFalse, CyTrue);

                    isHandled = CyTrue;

                }

            }

        }