USB superspeed peripherals Forum Discussions
Hi everyone, I'm sorry if my question is not for this thread. I'm working with Cypress EZ USB Suite software on different OS (Windows 7, Windows 10) and all of them have disabled GPIF button on the toolbar. GPIF II Designer works perfectly when I start it from desktop shortcut. But how can I fix GPIF toolbar button in the EZ USB Suite?
Show Lesshi,
FX-3 change packet size and burst rate in ISOC module (USBIsocSourceSink)
I would like to change the packet size and the burst at the same time in the ISOC module (USBIsocSourceSink)
in the 'cyfxisosrcsink.h' I'm changing 'CY_FX_ISO_MAXPKT' parameter from 1024 to 256.
I'm successfully program the FX3 but the device isn't enumerated.
i saw on another question that in order to chance the packet size we need to set "CY_FX_ISO_PKTS" to one. but this dont work for me as i need to send a burst.
is there any other parameter I should change in order to change packet size and burst rate at the same time?
Show LessDear Sir,
I'm using FX3S RAID-ON-CHIP USB DONGLE,
And Format of SD Card(4GB, HC, Class6) is possible in Windows10 OS.
But I can't format SD Card(16GB, HC, Class10) in Windows10 OS.
Why can't I format it?
If you have any modifications, please let me know.
I'd appreciate it.
Show LessHI Everyone,
The cyusb3014 in our board is self-powered through VBATT. The device cannot be renumerated after the usb cable reconnect while the VBATT power is kept.
I though this is caused by the firmware is running, and 3014 is not reset under this condition.
I add the following code to try solve the problem. But it didnot work. What di i do wrong?
In function SlFifoAppThread_Entry() the for loop:
void SlFifoAppThread_Entry(uint32_t input)
{
......
/* Initialize the slave FIFO application */
CyFxSlFifoApplnInit();
for (;;)
{
apiRetStatus = CyU3PGetConnectState(); //chech whether vbus is connected.
if(apiRetStatus == CyFalse)
glIsDeviceRemoved = CyTrue;
if(apiRetStatus && glIsDeviceRemoved) //if the vbus return to high voltage, then reset the CPU and rerun the fireware for PC enumerate.
{
glIsDeviceRemoved = CyFalse;
CyU3PDeviceReset(CyFalse);
}
}
}
I also tried the sample code in cyfxlowpowertest.c but it doesnot work. Maybe those reasons make it useless.
1. The CY_U3P_USB_EVENT_VBUS_REMOVED signal cannot be invoked by usb3.0 cable removed in
void CyFxApplnUSBEventCB (CyU3PUsbEventType_t evtype, uint16_t evdata).
2. The firmware cannot go into standby mode, because the peripheral blocks is not disabled with power on.
3. The suspendmode is not usefull because it need PC send cmd to cyusb3014.
4. The CY_U3P_SYS_UART_WAKEUP_SRC cannot be used because we use spi flash for 3014 boot, so the uart pin is used for SPI.
Show LessI would like to add a filter to the power pins below.
- VDD
- AVDD
- CVDDQ
Only the maximum current value is listed in the data sheet, but how much current flows per pin? I think that power domain with multiple pins carries the same amount of current. Is it correct?
I would like information to determine the constants of passive components.
Thanks,
Tetsuo
Show LessHello!
We using cx3 and ov5460 develop a UVC device,and refclk source is 27 MHZ.We want to use it in 2592*1944,3fps (usb 2.0), We don't know how to config the mipi parameters.we need help,thanks.
Show LessHi all, we try to create a BULK IN&OUT path between FPGA - CYUSB3014 and Android tablet(samsung), the firmware used in FX3 is "slave fifo example image" which support stream in & out function. IN data is generated by FPGA and transferred to FX3 buffer via GPIF-II, then Android host read data from FX3 buffer via USB 3.0. OUT data is a inverted way compared to IN data path. Android usb test program is based on "libusb" which has been intergreated in android system, when android receive a 16384-byte packet from FX3, it just drop it and ready to receive another one(for usb bandwidth test).
Before the Android test, we have successfully verified our FX3 slave fifo image by Cypress offical test tools (Streamer and Control Center), make sure the FPGA logic and FX3 image are OK.
In Android BULK IN test, we found a weird phenomenon, after several successfull packet receiving, the android program always blocked at "bulkTransfer()", this system function call a BULK IN transfer from host to FX3.
I have no idea if the host does not generate a right BULK IN request or the FX3 dose not response, because the "bulkTransfer()" is a system function and we have no way to debug inside it, but one thing can be sure that the data buffer in FX3 is full and FX3 reject data transferring from FPGA via GPIF-II.
any one help me to handle this problem?
Show LessHi all,
We're developing an in-house image sensor and using the FX3 for data streaming.
I want to know if the GPIF bus can handle different line lengths/sizes in the same frame, assuming we know the length of each line.
Is it possible?
Show LessHello,
Is there any limit in maximum resolution or line length over MIPI interface if throughput is less than 2.4Gbps?
I'm trying to configure CX3 to read images 7992x6000 RAW 10 bits and configuration tool does not give me any errors but I do not receive correct frames. The image sensor can oputput 8000x6000 but as I understand H active needs to be divisible by 24? If I reduce H active to 4000 or less it works, bit once I configure H active over 5000 it does not. Changing V active to lower values does not allow me to increase H active. Bellow are 2 configurations, the first one works just fine. Bellow are snapshots of configuration tabs. I'm using SDK version 1.3.3.
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Hi,
My problem is after configure uart dma rx transfer mode, i got every byte is zero in call back. my code is as below:
CyU3PReturnStatus_t
CyFxUartApplnInit (void)
{
CyU3PDmaChannelConfig_t dmaConfig;
CyU3PUartConfig_t uartConfig;
CyU3PReturnStatus_t apiRetStatus = CY_U3P_SUCCESS;
rst_cpld();
apiRetStatus = CyU3PUartInit ();
if (apiRetStatus != CY_U3P_SUCCESS)
{
CyFxAppErrorHandler(apiRetStatus);
}
CyU3PMemSet ((uint8_t *)&uartConfig, 0, sizeof(uartConfig));
uartConfig.baudRate = CY_U3P_UART_BAUDRATE_2M;
uartConfig.stopBit = CY_U3P_UART_ONE_STOP_BIT;
uartConfig.parity = CY_U3P_UART_NO_PARITY;
uartConfig.flowCtrl = CyFalse;
uartConfig.txEnable = CyTrue;
uartConfig.rxEnable = CyTrue;
uartConfig.isDma = CyTrue; /* DMA mode */
apiRetStatus = CyU3PUartSetConfig (&uartConfig, NULL);
if (apiRetStatus != CY_U3P_SUCCESS )
{
CyFxAppErrorHandler(apiRetStatus);
}
CyU3PMemSet ((uint8_t *)&dmaConfig, 0, sizeof(dmaConfig));
dmaConfig.size = 192;
dmaConfig.count = 4;
dmaConfig.prodSckId = CY_U3P_LPP_SOCKET_UART_PROD;
dmaConfig.consSckId = CY_U3P_CPU_SOCKET_CONS;
dmaConfig.dmaMode = CY_U3P_DMA_MODE_BYTE;
dmaConfig.notification = CY_U3P_DMA_CB_PROD_EVENT;
dmaConfig.cb = CyFxUacMicDmaCallback;
dmaConfig.prodHeader = 0;
dmaConfig.prodFooter = 0;
dmaConfig.consHeader = 0;
dmaConfig.prodAvailCount = 0;
apiRetStatus = CyU3PDmaChannelCreate (&glUartRXChHandle,
CY_U3P_DMA_TYPE_MANUAL_IN, &dmaConfig);
if (apiRetStatus != CY_U3P_SUCCESS)
{
CyFxAppErrorHandler(apiRetStatus);
return apiRetStatus;
}
apiRetStatus = CyU3PUartTxSetBlockXfer(0xFFFFFFFF);
if (apiRetStatus != CY_U3P_SUCCESS)
{
CyFxAppErrorHandler(apiRetStatus);
}
apiRetStatus = CyU3PUartRxSetBlockXfer(0xFFFFFFFF);
if (apiRetStatus != CY_U3P_SUCCESS)
{
CyFxAppErrorHandler(apiRetStatus);
}
apiRetStatus = CyU3PDmaChannelSetXfer (&glUartRXChHandle, 0);
if (apiRetStatus != CY_U3P_SUCCESS)
{
return apiRetStatus;
}
#if 0
/* Initialize the debug module. */
apiRetStatus = CyU3PDebugInit (CY_U3P_LPP_SOCKET_UART_CONS, 8);
if (apiRetStatus != CY_U3P_SUCCESS)
{
CyFxAppErrorHandler(apiRetStatus);
}
CyU3PDebugPreamble (CyFalse);
#endif
return apiRetStatus;
}
Callback code:
static void
CyFxUacMicDmaCallback(
CyU3PDmaChannel *chHandle, /* Handle to the DMA channel. */
CyU3PDmaCbType_t type, /* Callback type. */
CyU3PDmaCBInput_t *input) /* Callback status. */
{
if (type == CY_U3P_DMA_CB_PROD_EVENT && recording == CyTrue) {
nprintf("%d-> %x %x %x %x\r\n",
input->buffer_p.count,
input->buffer_p.buffer[52],
input->buffer_p.buffer[43],
input->buffer_p.buffer[74],
input->buffer_p.buffer[95]);
CyU3PEventSet(&glMicEvent, MIC_EVENT, CYU3P_EVENT_OR);
}
}
from the log (send back to pc via vcom port), data always be zero, length is correct
192-> 0 0 0 0
but from logic analyzer the data is not zero.
Is there anything wrong in configuration ? thanks.
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