USB superspeed peripherals Forum Discussions

Hi All,

I am writing firmware for the CX3 to interface a new sensor and am running into a confounding problem.  My program behaves differently when I rearrange the order of functions in my C source code.  This leads me to believe I have some memory corruption issues.  I found the CyU3PMemCorruptionCheck() and CyU3PBufCorruptionCheck() functions in cyu3os.h and am trying to use them in my program.  But when I do, the linker complains they are not defined.  In what library are they defined?

Thanks,

Scott

Our Image Sensor has MIPI CSI-2® v3.0  (September 2019).

But CX3 has MIPI CSI-2 compliant (Version 1.01).

Does CX3 suitable for our design?

Hi!

I have the following system: FPGA -> FX3(superSpeed explorer kit)->PC

I send counter from FPGA, but on pc i get shuffled data in multiples of packet size (1024)(1.png in attachments)

I try different parameters of DMA counts, DMA buffer size, but always the same

FX3 work on modified FIFO sync mode(from examples)

I'm not quite sure what other information to provide, so ask, I'll attach

Hi,

I'm trying to debug my FX3 program with J-Link but after download finishes nothing happens. Debugger not didn't stop "main".

At the same time if I try to debug some SDK example program (e.g. UsbUART) it works fine.

Here is J-Link output for my program:

And debugger windows shows:

Looks like it really running because I see device is recognized in my windows device manager.

But for some reason in doesn't stop neither at main, nor at any other breakpoint.

I'll greatly appreciate any help here

Things I checked so far:

1) Disabled entering to suspend mode

2) Added CPU frequency change at startup as per KBA229087

Hi,

I'm trying to use the watermarks to end the GPIF2 data transfers.

My FX3 design is a 32b slave FIFO with flagA as ready/empty and flagB as watermark (both thread dependent). When accessing the FX3 in RD mode (U2P), the watermark is working as expected and everything goes great.

When accessing in WR mode (P2U), for some reason, the watermark comes earlier than what I would expect. I'm sending a whole FX3 buffer (16KB) from my FPGA and counting the amount of data sent (in 32b words), so for now the watermark flag it is not at the FPGA side.

The watermark for P2U access is configured with a value of 6, so, according to the documentation, the flag should go down when there are 2 samples left to be sent. At the FPGA I'm double registering the watermark, so I'm expecting the watermark to become low when there is no more data to be sent. However I still see that, even after the 2 cycle delay, the watermark does not arrive where I am expecting it. 

I'm including the chip scope capture so you can have a look, as well.

The configuration for the FX3 watermark is as follows:

 Thanks in advance.

I have a question about Bulk Out transfer.

Currently I am using Bulk Out transfer to stream data into our logic.

The data to be sent is 0x80100 bytes for each Bulk Out transfer.

The source code of the application is shown below.

int MyXferBulkOut(unsigned char *dt, int length)
{

CCyUSBDevice *USBDevice;
CCyUSBEndPoint *OutEndpt;
bool success;
ULONG ret;
int instance;

USBDevice = s_USBDevice; // USB Device Object, when we are get on initialization.

OutEndpt = USBDevice->EndPointOf(0x02); // BulkOut EP2, Auto DMA, Buffer Count = 4
if (OutEndpt == NULL) {
return(-1);
}

OutEndpt->TimeOut = 5000;
success = OutEndpt->XferData( dt, length ); // length = 0x80100;

if (success) {
ret = 0;
}
else{
ret = -1;
}

return ret;
}

I have some problem.

After executing 0x80 100byte Bulk Out transfer with the XferData function in the above source code, immediately after the function returns
Bulk Out transfer the next 0x80 100byte data.

At this time, the length of data transmitted to our logic circuit is often shorter than expected.

The cause is completely from the EndPoint Buffer of EP2 to our logic circuit immediately after the XferData function returns.
Since it has not been flushed and the XferData function is called again in the above source code in that state,
This is because the previous data remains in the End Point Buffer of EP2 and the next Bulk Out transfer is instructed.
I'm guessing.

I have a few questions.

Q1. Is there any data left in the Endpoint Buffer immediately after the XferData function (BulkOut) returns?

Or does calling the XferData function transfer to EP2-> EP2's Buffer is completely flushed before returning?

Q2. If there is any data left in the EP2 Endpoint Buffer when the XferData function (BulkOut) returns, that is
How to check if it is empty?

Best regards.

Dear sir,

Now I am trying the develop a product with CYUSB3014, and I am reading 2 documents to help me understand it.

<<001-76074_EZ-USB_FX3_Technical_Reference_Manual.pdf>> and <<001-92220_AN75779_How_to_Implement_an_Image_Sensor_Interface_with_EZ-USB_FX3_in_a_USB_Video_Class_UVC_Framework.pdf>>

And I find a problem.

In the chapter 7.11 of Techincal reference manual, there is a flag named DMA_RDY_TH0. And DAM_RDY_TH1.

According to my understand, this flag is used to solve the GPIF's problem between data transfer and the DMA buffer switch in different thead. When the thread is swith to used a free DMA buffer, this flag is used to pause the data transfer.

So if the GPIF used 2 thread to receive the data, this flag should be used.

But in the AN75779, I did not find any information about this flag. So does it mean that there is a loss of data during the 2 thread switch in AN75779 example?

Thanks

Chad

Hi!

I'm looking for an example that streams parallel data back to a PC using the GPIF on an FX3. Does such an example exist? I'm attempting to build an SRAM sniffer.

Thanks!