USB superspeed peripherals Forum Discussions
I use FPGA and fx3's gpif ii to transfer data, when the external clock pclk is 100MHZ, it can be transferred normally, when change the pclk to other frequency lower than 100MHZ, the transfer data report error: BULK IN transfer failed with Error Code:997
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E8%B6%85%E9%AB%98%E9%80%9FUSB%E5%A4%96%E8%AE%BE/fx3%E7%9A%84gpif-ii%E7%9A%84pclk%E9%A2%91%E7%8E%87%E6%94%B9%E6%88%90%E5%B0%8F%E4%BA%8E100M%E7%9A%84%E5%85%B6%E4%BB%96%E9%A2%91%E7%8E%87%E5%9C%A8%E5%9B%BA%E4%BB%B6%E5%BD%93%E4%B8%AD%E8%BF%98%E9%9C%80%E8%A6%81%E8%AE%BE%E7%BD%AE%E4%BB%80%E4%B9%88%E5%90%97/td-p/700138
Show LessHi ,
In fx3 controller ,
During streaming ,an unexpected interruption occurred due to a stop request. As I checked, the stop request has been came from the host, not from my application I have been used. I have attached the usb log. kindly find the image (usb transaction image.png) .
In that image , during IN Transaction, before stop request occurs from host , I found that lup - 9182 , ldm -9385 , 810 itp value differs . During normal condition , lup - 15 or 14 or 13 , ldm - 15 or 14 or 13 , 1 or 2 itp. But before stop request came from host, lup,ldm,itp value differs. kindly check the image attached.
Then timing also differs during IN transaction. I have highlighted in image. After IN transaction which occurs in time 606.035 , the another IN transaction should occur.. but unfortunately it marked as error in IN transaction(not ready error) in timing 606.051.
Could you please explain why After IN transaction timing (606.035) , this much of lup - 9182 , ldm -9385 , 810 itp is occuring. Kindly check the timing in image i have mentioned.
kindly verify full transaction file i have attached (FX3_issue_infineon_trace.zip).
Please comment your suggestion.
Show Less您好,请教个问题,我们在设置flagA为currentThreadDMAReady,设置flag B为currentThreadDMAWarterMark,在cyU3PGpifLoad()下方调用CyU3PGpifSocketConfigure(0,CY_U3P_PIB_SOCKET_0,6,CyFalse,1),测试时,上位机不从USB取数,逻辑抓取信号发现flagA会被拉低,但是flagB一直是高,请问下可能是什么原因造成的呢?
Show LessMy application is that CyUSB3014's UART, GPIO55, and GPIO56 are directly connected to the FPGA. EP0 receives PC data, sends it to the FPGA through UART, and the data that UART receives in response from the FPGA is sent back to the PC via EP0. The transmitted UART communication is a 16 byte data frame, and the communication frequency is no more than 5 times per second. The problem currently encountered is that when the 3014 UART is configured in register mode, there is a high probability that a CY_U3P_UART_ERROR_RX_OVERFLOW error will occur, and communication cannot be restored. The UART callback function is as follows:
uart initialization function:
ep0 processing part:
There are currently no issues found. Then I tried the UART DMA mode again. There is no problem with UART RX, but there is a problem with TX. Sometimes TX fails to send, causing the FPGA not to receive data frames.
dma uart is initialized as follows:
cyu3preturnstatus_t uartDMA_sendData (uint8_t * buffer, unsigned int len) {cyu3preturnstatus_t status; unsigned int i = 0;
Cyu3PDMachannelGetBuffer (&gluarttXchHandle, glTxBuffer, 0); for (i = 0; i len; i++)
<
{
glTxBuffer->buffer[i] = buffer[i];
}
Cyu3PDMachannelSetupSendBuffer (gluarttXchHandle, glTxBuffer); status = &
Cyu3pdMachannelCommitBuffer (&gluarttXchHandle, 16, 0); return status;}
I don't know if anyone has run into this kind of problem?? thanks
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E8%B6%85%E9%AB%98%E9%80%9FUSB%E5%A4%96%E8%AE%BE/cyusb3014%E4%B8%B2%E5%8F%A3%E9%97%AE%E9%A2%98/td-p/649079
Show Less/* Class specific Uncompressed VS format descriptor */,how many resolution can be support in one format?when add to 0x39(/* Number of frame descriptor followed */), it can work well in windows but cannot be recognized as UVC camera in android,but reduce to 0x38, it can be recognized as UVC camera well in android。
Show LessHi,
Im trying to enable power management tab in FX3 driver. as you can see in the image below there isnt power management tab:
Im trying to enable Low power states in FX3 using example lowpowertest
This is what I expect to be look like
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你好:我现在能预览1600*1200分辨率的图像,但是用eCAM拍照功能,原有的分辨率都好使,我自己添加的分辨率1600*1200是黑屏,我用手机照射后拍照,发现有亮点,感觉是CyCx3_ImageSensor_Set_UXGA()这个里面缺少一些操作步骤,以及SENSOR_UXGAConfigurationSettings()缺少一些寄存器的设置,可能和AGC/AEC,有关,但是不知道怎么设置以及流程是怎么样的,希望帮助解决。
Show LessHello, our project uses USB3014 UVC. The EU unit can't do big data interaction, so I want to enumerate a CDC. Currently, I've modified the descriptor, and the CDC can successfully enumerate, but sometimes the host computer can't receive the data sent by 3014. The specific way to implement the CDC is as follows. First create two DMA channels, send event notifications in the callback, then process the DMA buffer in the EP0 thread, then send it back to the host computer. The code refers to UVC USB_DEBUG_INTERFACE and USBBulkLoopManualInOut, but sometimes the top players don't receive data. Please help me see where the problem is, thank you.
dma channel creation code
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E8%B6%85%E9%AB%98%E9%80%9FUSB%E5%A4%96%E8%AE%BE/CYUSB3014-UVC-CDC/td-p/665271
Show LessHello
I’m currently developing firmware to transmit image sensor (FPGA) from CX3 to U3V.
*Referenced the example : https://community.infineon.com/t5/Knowledge-Base-Articles/Implement-USB3-Vision-camera-with-EZ-USB-CX3-USB-3-2-Gen-1-device-controller/ta-p/445398
I was only testing in SuperSpeed, but when I tested in HighSpeed, I found that the Trailer comes before even all the data of one image is fetched. I thought this was happening because the speed at which the host fetches the image data and the speed at which the FPGA sends the image data do not match. So, I modified it to transmit one line from the FPGA and transmit dummy data, and then transmit the next line. However, no matter how long I give the dummy data, sometimes the partial buffer size is read differently when receiving the image.
Questions)
- Can you tell me about the situations where the partial buffer size can be different?
- Is the method to match the speed at which the host fetches the image data and the speed at which the FPGA sends the image data the control of Horizontal Blanking and Vertical Blanking?
- Is it correct that the LV signal goes low during the time of receiving dummy data?
- The sequence to receive one image is SWTrigger[0] -> Leader[0] -> image data[0] -> Trailer[0] from image 0. However, it is currently being delivered as SWTrigger[0] -> Leader[0] -> image data[0] -> Trailer[0] -> Leader[1]. Why is Leader[1] coming? Is it because of FV?
Image settings
- 1744x2400
- RAW14
- One image is transmitted per SWTrigger
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