USB superspeed peripherals Forum Discussions
Hello,i used project of USBVideoClassBulk and work on Windows10,and download firmware to ram of FX3 development board,windows10 camera could displays FX3 output image,but i download the same firmware to EEPROM of FX3 development board,then attached FX3 to ubuntu18.04,camera(cheese) couldn't identified device.
ubuntu18.04 dmesg dispaly as follows:
usb 4-4:new SuperSpeed USB device number 9 using xhci_hcd
usb 4-4:LPM exit latency is zeroed, disabling LPM.
usb 4-4:New USB device found, idVendor = 04b4, idProduct = 4722
usb 4-4:New USB device strings: Mfr = 1, Product = 2, SerialNimber = 0
usb 4-4:Product: FX3
usb 4-4:Manufacturer: Cypress
uvcvideo: Found UVC 1.10 device FX3 (04b4:4722)
input: FX3 as /devices/pci0000:00/0000:00:14.0/usb4/4-4/4-4:1.0/input/input22
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I have been using jLink debugger to debug my fx3 system for years without much problems, but recently I got a new laptop that give me some debug issues.
Sometimes when I have halted the CPU on a breakpoint, the connection with the CPU is kind of lost, i.e. I can't step or continue the execution. I suspect that it happens when looking at variable contents, especially large arrays.
Both computers are running Windows 10 with latest updates. I use the same version of Cypress EZ USB Suite and the Debug settings seem to be the same.
Any ideas on what could be causing this?
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Hi,
I am currently working with a CX3 in order to transfer data frame from a CIS sensor to the host.
I need to send some custom information with each frame for, but I don't know if it is possible to modify or add byte information into Payload Header or to the end of the frame.
Please could you give me same advice about how to do that? I guess I will have to modify the DMA buffer size in order to add byte information. But I would like to know if there are already some bytes that I can modify without to change the DMA buffer size.
Thanks.
Show LessHello all,
Our UVC camera device with FX3 rarely has USB disconnection issue.
Through analysis using USB3.0 Protocol Analyzer (Teledyne LeCroy T3), we noticed that after LBAD signal is sent from host just before disconnection, and FX3 did not retry sending same data three times as discribed in the USB3.0 Standards.
We already found a countermeasure for it, and it is that changing the corresponding bit from 0 to 1 of Link Interrupt Mask Register. (b3 of 0xE0033008)
Though this change derived good result in almost all test environments, it occured other issue in a particular environment. Specifically, data transfer failure.
My questions are below.
1. If someone faced and solved USB disconnection issues, if possible, please let me know your solution.
Of course, we disabled LPM to avoid very fast transition from U1 to U0.
2. If someone already tried to change "Link Interrupt Mask Register", please share the effect in your environment and how to set this register. I mean where in your source code, you set it.
Currently, we set this register at the bottom of "CyFxUVCApplnInit".
Thanks,
Kei
Show LessHi,
I have a FX3 firmware project with a working GPIF state machine configured with a manual DMA channel for GPIF to USB transfer (based on the sample cyfxgpiftousb).
The GPIF is able to produce a data package (1030 byte) up to every 60 microseconds. The interval time is configurable by the firmware.
If the data is ready, the DMA callback function is called, where I change some bytes from the buffer (add a counter) and then commit it with CyU3PDmaChannelCommitBuffer.
Now I want to commit the data only when a special firmware flag is set, otherwise I want to discard the buffer with CyU3PDmaChannelDiscardBuffer and not transfer it to the PC.
But this is working only if the interval is set to several milliseconds.
If the interval is set to lower values, so that e.g. the DMA callback is called every 1 millisecond, the buffer discarding seems to take too long, and the callback will not be called after some passes.
My question, does the discarding really takes so long or is there is something wrong on my thoughts.
void GpifToUsbDmaCallback(CyU3PDmaChannel *chHandle, CyU3PDmaCbType_t type,Show Less
CyU3PDmaCBInput_t *input) {
int i;
CyU3PReturnStatus_t status;
if (type == CY_U3P_DMA_CB_PROD_EVENT)
{
if(input != NULL && input->buffer_p.count > 0)
{
if (boTintChanged)
{
comm_PutChar (ACK);
CyU3PDmaChannelDiscardBuffer (chHandle);
boTintChanged = CyFalse;
}
else if (boFetch)
{
// The first six byte contains data garbage from the ADC pipe
// so we can change the first 4 byte and include a counter...
input->buffer_p.buffer[0] = uiDataSignature;
input->buffer_p.buffer[1] = uiDataSignature>>8;
input->buffer_p.buffer[2] = uiDataSignature>>16;
input->buffer_p.buffer[3] = uiDataSignature>>24;
uiDataSignature++;
// ...and set the next two byte to zero (preserved for future usage)
input->buffer_p.buffer[4] = 0;
input->buffer_p.buffer[5] = 0;
CyU3PReturnStatus_t status = CyU3PDmaChannelCommitBuffer (chHandle, input->buffer_p.count, 0);
CyU3PDebugPrint(4, "GpifToUsbDmaCallback CyU3PDmaChannelCommitBuffer %d \r\n", status);
boFetch = CyFalse;
}
else
status = CyU3PDmaChannelDiscardBuffer (chHandle);
}
else
status = CyU3PDmaChannelDiscardBuffer (chHandle);
}
if (type == CY_U3P_DMA_CB_CONS_EVENT)
{
/* Data transfer has been started. Enable the LPM disable loop. */
}
CyU3PDebugPrint(4, "GpifToUsbDmaCallback Event %d empfangen \r\n", type);
return;
}
Dear all, (and @YatheeshD_36)
Almost 18 months ago I was having some issues in using the .Net Api for Cypress EZ-USB FX3 SDK.
However I got some really nice help in this thread:
https://community.infineon.com/t5/USB-Low-Full-High-Speed/SuiteUSB-using-NET-API-for-PassMark-USB-3-0-plug/m-p/76716#233780
The issue was resolved and everything has been running smoothly for the last 18 months until the other day.
What has changed? Nothing obvious that I'm aware of, but our IT department has updated machines with Windows security patches if that could make a difference.
What seems to happen is the following:
- The device (Passmark USB3.0) inserted into the machine.
- My code is using the CyUSB .Net interface for the CyUsb3.sys driver.
- My code checks that the endpoints are USB 3.0 by checking the size of the MaxPktSize of the endpoint and making sure that it is not below 0x4000.
- This is all good. Then my program creates an arbitrary buffer of 65k data and calls the
endpoint function XferData. - This fails and if I debug fairly deep down in CyEndPoints.cs (at line 367 in function BeginDataXfer) I can see that _lastError is set to 997. The function returns a true so this might be as expected.
- After this the function FinishDataXfer is called to get the overlapped result. However the rResult from the GetOverlappedResult function returns false and the len is set to 0 bytes.
- No bytes are being transmitted.
- One observation is that after the device was inserted the Cypress Control Center reports a descriptor info with a Bulk channel with MaxPktSize of 16384.
- After the transmittal failure the device info reports just a bulk channel of 1024 bytes (which is what I interpret as HS instead of SS)
- However the device still seems to be enumerated at SS from what it will let you know through its display.
(The Passmark testprogram does not show any errors and happily runs at SuperSpeed (USB3.0))
- There have been no code changes for my code.
- From what I can tell there are no updates to the Cypress / Infineon SDK (EZ-USB FX3 SDK 1.3.4 for Windows)
- There are no updates to the FW of the Passmark adapter nor to their driver during the last 18 months.
If someone has any idea what I should try to look further into, or has any advice on how to move forward, it would be greatly appreciated.
King regards
Magnus
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We are seeking paid assistance to solve a communication problem between the Cypress FX3 and computers using USB 3.0. We have written some custom code that gets the buffer contents in a loop. We have installed Cypress driver CYUSB3.SYS version 1.2.3.20
With this code, we are able to transfer 1GB data in about 8 sec on an HP Z440 computer running Windows 7 running CYUSB3.SYS 1.2.3.3, and on several other computers running Windows 10.
However, when we try to run on our Lab computer, a Dell Xeon W-2125 4GHz with 64GB RAM, x64-based processor, communication times out above 512K data, and inserts a 10 sec delay. This delay is inserted multiple times depending on the data size. We can affect this problem by slowing down the capture loop by inserting internal looping to take up processing time, but this isn't a solution
We are requesting assistance in a proper solution to this problem
Hi, I'm designing a PCB with CyUSB3014 and an FPGA; the application note AN170707 (hardware design guidelines and schematic checklist) says that I have to put a 22 ohm series termination resistor on each line of GPIF interface in order to avoid reflection, but most of GPIF lines are bidirectional, so where should I put the resistors? Should I put that closer to the FX3 or to the FPGA?
Can I use the DCI (Digitally Controlled Impedance) technology of Xilinx FPGA instead of putting resistors on the PCB?
Why should I put 22 ohm if my traces on PCB are 50 ohm? Isn't it better to put 50 ohm?
We send data of FPGA wirelessly(WIFI) through FX3 ,use USB port of the FX3 HOST mode ,
Whether FX3 supports the TCPIP protocol stack and How much bandwidth can I get?
Show LessHello.
I have a question about how to use FX3 USB3.0 SlaveFIFO 5Bit address and EPSWITCH.
As shown in the picture below, I have configured 6 endpoints.
FIFO ADDRESS : 0x1~0x3 = Bulk In endpoint(0x81~0x83)
FIFO ADDRESS : 0x5~0x7 = Bulk out endpoint(0x01~0x03)
FIFO address: 0x1~0x3 = Bulk In endpoint (0x81~0x83)
FIFO Address: 0x5~0x7 = Bulk Out Endpoint (0x01~0x03)
In this configuration, if EPSWITCH is set to '1' and data is transferred to the bulk out endpoint (0x01), a Flag signal is generated in FIFO ADDRESS 0x1 inside the FPGA as shown below.
If you think about it, why is the FLAG signal that only occurs at FIFO ADDRESS 0x5 occurs at FIFO ADDRESS 0x1 and FIFO ADDRESS 0x5?
When data is transmitted to the endpoint (0x02), a FLAG signal is generated at FIFO ADDRESS 0x2 and FIFO ADDRESS 0x6.
FIFO Address: Flag signal from 0x1 to 0x3 is '1' and should be changed to '0' when sending data from FPGA.
FIFO address: The flag signal of 0x5~0x7 is usually '0', but when sending data from the PC, the flag signal of the corresponding FIFO address must be changed to '1'.
I looked at the datasheet and used EPSWITCH, but it doesn't work as expected.
SlaveFIFO read and SlaveFIFO write must be repeated continuously.
Can you tell me the correct way to use EPSWITCH to use FIFO address: 0x1 ~ 0x3 as SlaveFIFO read and FIFO address: 0x5 ~ 0x7 SlaveFIFO write?
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