USB superspeed peripherals Forum Discussions
Hello all,
I need to start a slave device which has SPI control lines interfacing with FX3 (CYUSB3KIT-003) with separate data lines (D0...D8) something. I am using SDK1.3. Is there any example which refers to the SPI control only operation with FX3?
Which mode is better to go with FW control or GPIO?
Please suggest~
Thanks
Best Regards,
/Ash
Show LessHi all,
I am looking for USB FX3 SDK version 1.3.5 as mentioned in KBA218830,but i can just find version 1.3.4 from the following link: https://softwaretools.infineon.com/tools/com.ifx.tb.tool.ezusbfx3sdk.
Any idea where I can find FX3 SDK version 1.3.5?
Thanks!
Show LessI have problem to discard DMA buffer.
I'm receiving data using isochronous transfer.
I have tested data receiving GPIF to USB isochronous transfer mode. DMA buffer has always previous received data. I want to clear this data and receive new data from the first.
"Start reviving data >> Stop receiving data >> Clear DMA buffer >> Restart receiving data"
I added control command to discard DMA buffer. But it returns error message.
How to discard DMA buffer GPIF to USB isochronous transfer mode.
I attached source code. Please review this code to solve this problem.
Show LessHello,
Is the FX3 (CYUSB3014) limited on the above mentioned SPI flash devices? Is it possible to use existing SPI flash in control center and other related functions with other SPI flash devices i.e., W25Q64JVSSIM?
Thanks and regards,
jl46
你好:
请问我用上位机控制cyusb3014传输数据,每次初始化*USBDevice指针时,都会消耗很长时间,大概15-20ms左右呢?以下是上位机初始化的程序。
CCyUSBDevice *USBDevice = new CCyUSBDevice();
CCyControlEndPoint *ept = USBDevice->ControlEndPt;
CCyUSBEndPoint *ept_in = USBDevice->EndPoints[2]; //控制端点0x81接收
Show LessHi,
I'm using the FX3 to interface with 3 10-bit image sensors and send the data via USB. Sensor data is synchronized into a 30-bit word via an FPGA connected to 32-bit GPIF interface using standard video signal controls.
The application works correctly as long as there is no a stop/start cycle. After a cycle, the error CY_U3P_ERROR_TIMEOUT is randomly returned in the CyU3PDmaMultiChannelGetBuffer routine called inside the CyFxUvcApplnDmaCallback.
When this error occurs, GPIF data is lost because the total number of bytes at the end of the frame is less than expected.
What would be the reason for a timeout error to occur when accessing a DMA buffer in the event that indicates that there is a buffer ready for reading?
Below can be seen the code snippet where the error occurs.
void CyFxUvcApplnDmaCallback(CyU3PDmaMultiChannel *chHandle, CyU3PDmaCbType_t type, CyU3PDmaCBInput_t *input)
{
CyU3PDmaBuffer_t dmaBuffer;
CyU3PReturnStatus_t status = CY_U3P_SUCCESS;
if (type == CY_U3P_DMA_CB_PROD_EVENT)
{
status = CyU3PDmaMultiChannelGetBuffer(chHandle, &dmaBuffer, CYU3P_NO_WAIT);
//... (Original code of AN75779)
}
//... ... (Original code of AN75779)
}
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I am using the AN75779 firmware code. When I add a new extension unit and modify the connection between the different units, Windows recognizes the device I am working on as a camera (I opened the device manager and found the device "FX3")
However, I can not access it from any program.
Here is the extension unit descriptor
It is not clear to me what the problem is. Please help!!!!
Thank you in advance
Show LessHello, I encountered some problems in the process of reading and writing FPGA and FX3. I want to clarify, the configuration is as follows:
The size of the buffer is set to 16kB
The data bus bit width is 32 bits, and the watermark value is 6,
The state machine is sync slave fifo state machine
FLAGA: Thread_0_DMA_Ready
FLAGB: Thread_0_DMA_Watermark
FLAGC: Thread_3_DMA_Ready
FLAGD: Thread_3_DMA_Watermark
1. The size of my upstream buffer is 4*16KB. FLAGA is configured as a dedicated thread flag Thread_0_DMA_Ready. The FLAGA in the data sheet indicates the current state of the buffer (that is, whether the buffer is full, 0 means full, 1 means dissatisfaction), but when I send a short packet For example, at 32B (the timing is that slwr is pulled down for 32 cycles, and pktend is pulled down for one cycle), I can still see FLAGA from high to low (pulled down by about 11μs). Specifically, the size of a single buffer is 16KB. At this time, only 32B is written, and the buffer is definitely not full. Why FLAGA will change from high to low. When I write 1024B (the timing is to send 256 cycles of data plus a zero packet), the same phenomenon occurs. Will FLAGA be pulled down from high every time I commit?
2. The bit width of my data bus is 32 bits. I would like to ask whether the smallest unit of data sent each time is 4B (32bit). I use short data packets to send 30B from FX3 to FPGA (when data is not a multiple of 4B). Errors will occur, is there a requirement for the size of the data?
3. When the FPGA writes to FX3, when the size of the data is 1024B, I tested two methods, one is in the form of short data packets, the other is by sending a zero-length data packet (ZLP), both methods can be passed I can see the correct data from the control center. Can these two methods work?
4. When the FPGA writes to FX3, when the size of the data is 16KB, two tests are done. First, the PKTEND signal can be raised all the way, and the commit can be made. The second use of the short data packet form (that is, when the last bit of data is 16384B, pull down the PKTEND signal), I can also see the correct result. May I ask whether this situation is normal.
5. With the example code provided by AN65974, when FPGA reads data from FX3, a tap operation is required. May I ask if this is necessary?
Show LessI'm trying to debug firmware written for a board with a CYUSB3035 FX3 IC using openOCD and a Digilent HS2 JTAG adapter. Because the bundled config is written for an older version of openOCD and a different interface, I have modified the config accordingly. I make sure the device is in bootloader mode, but when I run `openocd -f <my.cfg> -c init`I encounter errors. It's a custom board, but the hardware seems alright since I've gotten the bulk loop example and several others to work on the board.
The modified config file is as follows (I have attached a zipped copy)
#
# OpenOCD configuration file for Cypress FX3 (ARM926EJ-S).
#
# FX3 has a standard ARM JTAG TAP and can work with a standard ARM926EJ-S configuration.
#
# The interface selected below is the CY7C65215 based JTAG debug probe. If another
# debug probe is being used, just replace the "interface cy7c65215" line with the
# appropriate interface name.
#
gdb_port 3333
adapter driver ftdi
ftdi_device_desc "Digilent USB Device"
ftdi_vid_pid 0x0403 0x6014
ftdi_channel 0
ftdi_layout_init 0x00e8 0x60eb
reset_config none
transport select jtag
######################################
# Target: CYPRESS FX3 ARM926EJ-S
######################################
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME fx3
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x07926069
}
#delays on reset lines
adapter srst delay 200
jtag_ntrst_delay 200
adapter speed 1000
reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag_rclk 3
######################
# Target configuration
######################
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
adapter speed 1000
Is there an error in the way I've connected to or configured the hardware, or is there some mistake or omission in my configuration?
If I ground TSRST I get the following errors, and if I attempt to attach gdb I get further errors
Open On-Chip Debugger 0.11.0+dev-00103-gff755a575-dirty (2021-04-20-10:11)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1000 kHz
Info : clock speed 1000 kHz
Error: JTAG scan chain interrogation failed: all ones
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway...
Error: fx3.cpu: IR capture error; saw 0x0f not 0x01
Warn : Bypassing JTAG setup events due to errors
Info : Embedded ICE version 15
Error: unknown EmbeddedICE version (comms ctrl: 0xffffffff)
Info : fx3.cpu: hardware has 2 breakpoint/watchpoint units
Warn : WARNING: unknown debug reason: 0xf
Warn : ThumbEE -- incomplete support
Info : starting gdb server for fx3.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Error: Couldn't calculate PC of next instruction, current opcode was 0x00000000
If I leave it pulled up I get repeated errors till I try to attach a debugger and then it complains about not being halted. If I load a program into memory and try to enter commands into gdb I get further errors about the CPU not being halted. it seems similar to this question . Any help you could provide would be much appreciated
Error: unknown EmbeddedICE version (comms ctrl: 0x00400000)
Info : fx3.cpu: hardware has 2 breakpoint/watchpoint units
Info : accepting 'gdb' connection on tcp/3333
Error: timed out while waiting for target halted
Error executing event gdb-attach on target fx3.cpu:
Warn : GDB connection 1 on target fx3.cpu not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Warn : target not halted
Info : Halt timed out, wake up GDB.
Warn : target not halted
Warn : target not halted
Info : target fx3.cpu was not halted when step was requested
Show Less