USB superspeed peripherals Forum Discussions
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Hi,
I added LD_ctrl_count and used count_ctrl in my GPIF state machine. Then I used the CYU3P_GPIF_EVT_CTRL_COUNTER in a callback in firmware application(CyU3PGpifRegisterCallback (CyFxGpifCB);). But no event is received. I expected that when crtl_counter reaches to limit, I get an event.
My question is: should I active any other things for receiving counter’s events in GPIF SM?
I couldn't find any example using CYU3P_GPIF_EVT_CTRL_COUNTER or other counters.
For another test, I used the attached project in https://community.infineon.com/t5/USB-superspeed-peripherals/FX3-CyU3PGpifInitCtrlCounter-API/td-p/233814 . I ticked "reload counter on the reaching limit" in LD_ctrl_count and used
if (event == CYU3P_GPIF_EVT_CTRL_COUNTER) in CyFxGpifCB, then it doesn't work.
Actually I don't want to use CPU_int, I want to get the event by CYU3P_GPIF_EVT_CTRL_COUNTER.
Thanks
We have a system where several hubs and downstream USB switches are used. The hubs is a CYUSB3314-88LTXI.
The specification seems to require capacitors on the transmit pairs (in my case I would need them on all lines) and the specification uses the word "shall" implying that this is not optional at all.
Do any of you know whether I need them with certainty please ?
Thanks,
Ian
Show Lessslfifosync example code is running in Manual mode.
Which part of the codes in cyfxslfifosync.c (slfifosync example) represent the "Callback function invoked at end of transaction" by Consumer (Egress) Socket ? illustrated in FX3_PROGRAMMERS_MANUAL page 77.
Show LessHello,
I am working with the FX3 development board with 2 different camera module. For the start i used the OV7670 camera module, and it is working properly. Currently I try to use another image sensor which has a 400*400 10 bit raw output for that I modified the descriptors and the GPIF counters to 8183. Debug prints shows less than the half of the frames arrives also wireshark traces shows the same out come onl y 9 full buffer arrives. Vsync and Hsync signals were checked on oscilloscope, based on the clock signals(VSYNC 30Hz) it should be 30 frames. I attached all the results. I am bit clueless what could be the problem. (Yellow line VSYNC, HSYNC purple)
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I am working on a custom board with a CX3 chip to interface an OV5647 sensor with a computer. The GPIO pins that are meant for the UART interface have all been left unconnected and as a result I cant use the UART interface for debugging purposes. Is there any way to do the same action via the USB interface directly?
Show LessHi Cypress,
The example provided in slfifosync is example implements with two DMA Channels in MANUAL mode. Do you have example code for slfifosync running on Auto Channel with Signaling?
Show LessHello.
I've noticed that sometimes the USB endpoint communications locks up when a CYU3P_USBEP_SS_RESET_EVT occurs in the FX3 SDK 1.3.4. My firmware handles the event by stalling the endpoint similar to the examples provided. The only recovery I've found is to unplug/re-plug. I tried resetting the endpoint, flushing memory, destroying DMA channels, etc. Nothing could recover the FX3 endpoint. I started troubleshooting to find the root cause.
I tracked down the problem to somewhere in the libcyfxapi.a library in FX3 SDK 1.3.4. (I am using the pre-built library in Cypress\EZ-USB FX3 SDK\1.3\fw_lib\1_3_4\fx3_release\libcyfxapi.a) I then built that library myself from the 1.3.4 SDK source files. When I build the library myself using the gcc tool suite (I do not have the RVCT tool suite), the problem goes away with my gcc built library.
I tracked down the problem to the file cyu3usbpp.o in the pre-built library. I was able to extract the cyu3usbpp.o file from the pre-built libcyfxapi.a (dated 5/23/2018) and substitute that cyu3usbpp.o into my gcc built library. The problem tracks with the cyu3usbpp.o file from the pre-built library.
By carefully substituting functions from the pre-built library into my gcc build I was able to isolate the problem to the CyU3PUsbEpPrepare() routine in the pre-built library. The CyU3PUsbEpPrepare() is called from CyU3PUsbResetEndpointMemories() which happens upon a CYU3P_USBEP_SS_RESET_EVT event.
This is where it gets interesting. I found that the CyU3PUsbEpPrepare() function in the pre-built libcyfxapi.a library does not call CyU3PUibSocketInit() upon entry (whereas the source code does). Additionally, I found that if I remove the CyU3PUibSocketInit() call from my gcc built library, the problem occurs in my gcc built library as well. Additionally, the problem occurs with the 1.3.3 SDK libraries which also are missing the CyU3PUibSocketInit() call.
Here are my questions:
1) Why is the function CyU3PUsbEpPrepare() different in the pre-built libcyfxapi.a library versus the supplied source files?
2) Since I do not have the source code for the function CyU3PUsbEpPrepare() that is in the pre-built libcyfxapi.a file, is that the only difference in the library versus the supplied source code?
3) Does it make sense that missing the CyU3PUibSocketInit() call upon entry to the CyU3PUsbEpPrepare() function, that the FX3 could never recover that endpoint communications?
4) Is it possible to get pre-built libraries that match the supplied source code in the SDK.
Frank
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Hello,
I've still been working for an issue of the post.
Thank you for Infineon's supports for the post.
The topic was closed while I was working on some another FPGA issues on my product but
I found that the reason of the issue was confliction between transfers of two end points.
It seems that a GPIF II -> USB Bulk IN transfer is interrupted by a UART -> USB Bulk IN transfer.
------------
My product uses several Bulk IN channels,
1) GPIF II -> USB (to transfer large amount of data from external FPGA with high transfer rate continuously)
2) GPIF II -> USB (to transfer up to 32KB data from external FPGA occasionally)
3) UART -> USB (to transfer 32bytes fixed length short data from external MCU occasionally)
4) FX3 -> USB (to transfer debug print messages generated in FX3 occasionally)
These channels are polled by PC application asynchronously.
I found that attempts of XferData() for UART -> USB channel always ended with timeout.
The external MCU sends packets only occasionally and the FX3's buffer is empty most time.
No timeout is seen when a packet is sent from the MCU and FX3's buffer is filled.
I checked to call XferData() separately for each one of these 4 channels and
only UART -> USB channel had this issue.
(and the issue of the post is solved by not using the UART -> USB channel and GPIF II->USB channel simultaneously)
I would like to confirm that
1) Is this behavior of UART->USB port normal?
Or should the FX3 response ZLP (or something) immediately when the buffer is empty?
2) Is it possible to use XferData() "by two or more threads" "asynchronously"
"for different endpoints" of "one FX3 device"?
I read KBA94607 and it's possible with my understanding, but it's still not clear for me.
------------
I attach a wireshark log of USB transfer attempts.
The address of my FX3 product is 1.14. The UART->USB channel is 1.14.3 (EP 0x83).
Most polling attempts end with timeout in the log, however,
line 326 - 347 are intended data transfers and no problem is seen.
1) GPIF II -> USB, 4)FX3->USB channels are not activated to clarify the issue.
Address 1.14.2 is the 2)GPIF II->USB channel.
The UART channel setting is as shown below.
----------
UART Initialization
apiRetStatus = CyU3PUartInit();
if (apiRetStatus != CY_U3P_SUCCESS)
{
DebugPrint("UART_Initialize, CyU3PUartInit Failed, Error code = %d\n", apiRetStatus);
CommandErrorHandler(apiRetStatus);
}
//UART Settings
CyU3PMemSet ((uint8_t *)&uartConfig, 0, sizeof (uartConfig));
uartConfig.baudRate = CY_U3P_UART_BAUDRATE_115200;
uartConfig.stopBit = CY_U3P_UART_ONE_STOP_BIT;
uartConfig.parity = CY_U3P_UART_NO_PARITY;
uartConfig.txEnable = CyTrue;
uartConfig.rxEnable = CyTrue;
uartConfig.flowCtrl = CyFalse;
uartConfig.isDma = CyTrue;
apiRetStatus = CyU3PUartSetConfig (&uartConfig, NULL);
//Set the UART transfer to a really large value.
apiRetStatus = CyU3PUartTxSetBlockXfer (0xFFFFFFFF);
//TEST
CyU3PUartSetTimeout(1,1); // this did not affect the behavior of the channel
-------------
EP Initialization
CyU3PEpConfig_t epCfg;
CyU3PReturnStatus_t apiRetStatus = CY_U3P_SUCCESS;
CyU3PMemSet ((uint8_t *)&epCfg, 0, sizeof (epCfg));
epCfg.enable = CyTrue;
epCfg.epType = CY_U3P_USB_EP_BULK;
epCfg.burstLen = 0; //Burst length 1
epCfg.streams = 0;
epCfg.pcktSize = size;
apiRetStatus = CyU3PSetEpConfig(EP_COMMAND_CONSUMER, &epCfg);
if (apiRetStatus != CY_U3P_SUCCESS)
CyU3PUsbFlushEp(EP_COMMAND_CONSUMER);
--------------
DMA Initialization
CyU3PDmaChannelConfig_t dmaCfg;
CyU3PReturnStatus_t apiRetStatus = CY_U3P_SUCCESS;
dmaCfg.size = 32;
dmaCfg.count = 8;
dmaCfg.prodSckId = CY_U3P_LPP_SOCKET_UART_PROD;
dmaCfg.consSckId = EP_COMMAND_CONSUMER_SOCKET;
dmaCfg.dmaMode = CY_U3P_UIB_SOCKET_CONS_3;
dmaCfg.notification = 0;
dmaCfg.cb = NULL;
dmaCfg.prodHeader = 0;
dmaCfg.prodFooter = 0;
dmaCfg.consHeader = 0;
dmaCfg.prodAvailCount = 0;
apiRetStatus = CyU3PDmaChannelCreate (&glCommandIN_DMA_Handle,
CY_U3P_DMA_TYPE_AUTO, &dmaCfg);
apiRetStatus = CyU3PDmaChannelSetXfer (&glCommandIN_DMA_Handle, 0);
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目前采用CYUSB3014+FPGA的方案,在usb3.0接口下已经跑通;现需要兼容usb2.0接口,固件和驱动或者其他方面需要进行哪些修改才能兼容?
I am working on a custom board which makes use of the Cypress CX3 MIPI to USB bridge to interface a raspberry pi camera ver2.1(sensor- Sony IMX219PQ) with a single board computer running ubuntu 18.04. I was able to configure the chip to be recognized as a UVC video device by the edge computer. But when I try to stream from the camera using UVC video compatible apps like VLC media player, GUVCView and Xawtv I only get a black screen. When probing PCLK, H_Sync and V_Sync, I found that PCLK is the expected 72MHz clock whereas H_Sync and V_Sync are dead signals with no change. Note: The device is only able to use the USB2.0 interface. How do i troubleshoot this issue and proceed forward? |