USB superspeed peripherals Forum Discussions
I'm creating a new question because it turned out that my old one didn't have the right answer after all, and it's locked now so I can't change it.
I have 4 endpoints that are set up as auto channels, with DMA notifications. They work great.
I tried to set up a fifth endpoint to do some logging from the DMA callback via a manual out endpoint. I've determined that it is seeing the new data every time a buffer is filled from one of those endpoints, and it's output works for 39 entries that I can see on the host, but then it stops working. Every time I try to call CyU3PDmaChannelGetBuffer after that, it fails with a CY_U3P_ERROR_MUTEX_FAILURE.
Show LessThanks for helping, but I encounter three issues while doing FPGA writing to slavefifo, the firmware is the Stream_in image file and the setting is default as it mentioned in AN65974.
1. After reading AN65974, I still can't understand the relationship between FLAGB and watermark, please explain to me.
2. FLAGB drop to low while FLAGA remaining high, what does it mean?
3. Although the issue above is not fixed, the USB host can still receive the data from FGPA after using Xferdata, but FLAGA and FLAGB will become low and not reset to high automatically, does that mean I have to reset the DMAchannel by using CyU3PDmaChannelReset?
The Appendix are the initial state and after writing data(Can't receive data this time).
Thanks a lot.
Regards,
Daniel
Show LessHi EZ-USB team,
Based on the the dialog box provided by control endpoint in Control Center. How should i fill up the box for a I2C device with adress 0xA0 (7 bits from the left are the address and 1 bit from the right is read/write).
Reg code = 0xC1
wValue = ?
wIndex = ?
Direction = In
Bytes to Transfer = 8
I try to set wValue = 0xA0, but i get responce as follow:
CONTROL IN transfer
0000 FF FF FF FF FF FF FF FF
CONTROL IN transfer completed
Here are the Handle supported vendor requests we implement for I2C read.
case 0xC3:
CyU3PMemSet (glEp0Buffer, 0, sizeof (glEp0Buffer));
status = CyFxUsbI2cTransfer (wIndex, wValue, wLength, glEp0Buffer, CyTrue);
if (status == CY_U3P_SUCCESS) {
status = CyU3PUsbSendEP0Data(wLength, glEp0Buffer);
}
break;
Show LessDear sir,
My reference is AN65974, my case for FPGA write to USB is not a continuous data, instead it's a buffer, size of 4k bytes.
After transferring, and receiving the data, FlagA and FlagB remain low. What should I do to pull up the Flags?
I tried to reset the endpoint but it still can't work anyway.
Does this issue happen because of the wrong signal from FPGA, or I just need to clean the channel by vendor command?
Best Regards,
Daniel
Show LessDear members
I am developing USB3.0 function and beginner engineer.
Help me~~
[Symptoms ]
1. The unstable connection and disconnection status
Please let me know about the checking point hardware and software.
Chipset : CVUSB3014
Thanks
Dear sir,
My reference is AN65974. I can't figure out how FX3 API works in the firmware cyfxslfifosync.c.
There are many functions define in this cpp, but only a few of them are used in the main function, so I don't know how these functions work, such as CyFxApplicationDefine function which creates the threads, where is it being used?
Another question is the CyFxSlFifoApplnStop function. It says that can be called whenever a reset or disconnect event is received from the usb host. What does the reset event mean? Reset the usbdevice or endpoint?
Show LessHello,
We designed FPGA part of the data accusation device. Now we trying transfer the accused data to PC via EZ-USB SX3.
The FPGA signal interface timing diagram shown on the attached file. We are planning to use Stream IN approach. For current application, FIFO buffer is 1024bytes.
According 'AN65974 Designing with the EZ-USB™ FX3 slave FIFO interface', the time taken for the DMA channel to switch to the next buffer is not deterministic, although it is typically a few microseconds. The external master must monitor the flag to determine when the switching is complete and the next buffer has become available for data access.
From the AN65974 the FLAGA and FLAGB timing relation to the SLWR# not clear for Stream IN application. Could you please, provide the documentation and information regarding the FLAGA and FLAGB timing.
Sincerely,
Shamsi
I use Reset function which is in the CyAPI to reset the endpoints, does the effect is equal to CyU3PDmaChannelReset function which is in the FX3 API?
For all I know, the FX3 API is used in EZUSB Suite and produce an image file which has to burn to the FX3, so I'm not sure about whether the function in FX3 API can be used individually by Suite just like I use CyAPI in VS.
Thanks a lot.
Show LessThe following is stated in the datasheet. "The MAC core also implements CRC-32 checking at full-speed using a multi-stage, cyclic redundancy code (CRC) calculation architecture with optional forwarding of the frame check sequence (FCS) field to the user application CRC-32 generation and append on transmit." How is this option setup? Is it in the driver once installed and anabled by user or programmed on the eeprom? If so, where on the eeprom?
Show LessHello,
I am experimented the FX3 development board and an OV7670 camera, i was able to alter the AN75779 project based on the UVC and FX3 documentation. Now i have a custom UVC board with an FX3 IC, based on the experiences with the OV7670 I made some modifications:
- GPIF
- data bus 8bit->16bit
- LD_ADDR_COUNT: change to 8183
- LD_DATA_COUNT: change to 8183
- cyfxuvcdscr.c file
- width and height modified to 400*400
- Format changed YUY2 to MJPEG
- Changed bit rates, fps to 30 fps
- uvc.c
- changed the I2C address for configuring the sensor
- Changed the pwm for generating clk for the image sensor
Now I only capturing black frames, i checked the the clock signal and read out some register values via i2c, also checked the device in wireshark, and USB device viewer. Device is enumerating as a UVC device descriptors are OK, generating the clock signal, i2c communication works well, and the wireshark says the UVC requests works well.
But I all i got is black screen. I would appreciate any kind of help, try to find out the problem about 2 weeks.
Best regards
Show Less