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USB Superspeed Peripherals

ArGa_2874246
New Contributor

Hi All,

We are facing an issue with reading the data from SPI Flash using CX3.

SPI Flash Part Number - SST25PF040C (Microchip)

Please find the issue description below.,

Description :

On long-term usage, somehow the BPL bit in status Register of SPI Flash has changed to '1' and after that the Cypress Bootloader fails to read the Data from SPI Flash. To recreate this issue, we are manually setting the BPL bit to '1'.  

When the BPL bit of SPI flash is set to '1', the bootloader Firmware in CX3 Chip fails to read the data in SPI Flash and falls back to "Cypress FX3 USB Bootloader Device". 

BPL bit StatusBehaviour
1CX3 is unable to Boot From SPI Flash
0CX3 is able to Boot From SPI Flash

pastedImage_0.png

pastedImage_11.png

Our Findings :

  1. A Firmware to read the whole 512KB in SPI Flash is flashed in RAM.
    1. In this case, Read is successful and we can find that valid Firmware is present in SPI Flash.
  2. Using the Second stage Bootloader Firmware available in "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\boot_fw\src".
    1. In this firmware, the SPI _BOOT macro was defined to boot from SPI Flash.
    2. The Firmware can successfully transfer the data from SPI flash to RAM and can boot as a video device.

From the above findings, we can conclude that,

  1. On changing the BPL bit to '1', read works Fine. But only the Cypress Bootloader Firmware present in the chip is unable to read the data from SPI Flash.

Questions :

  1. Why the Bootloader Firmware present within the Chip is unable to boot from SPI Flash?
  2. Can anyone help me with finding actual source code of Bootloader firmware present in the CX3 chip?
  3. Why setting the BPL bit to '1' affects the Bootloader firmware to Read the data from SPI Flash? Whats the Difference in setting the BPL bit to '1' or '0'? 
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1 Solution
SrinathS_16
Moderator
Moderator

Hello,

- FX3 boot-loader samples the SPI lines during boot-up to identify the number of address bytes. If it samples the MISO line to be logic HIGH (or) floating, it stops sampling the line further for address cycles. Hence, it is essential that the MISO line stays LOW until the FX3 boot-loader identifies the address cycles.

- FX3 second stage boot-loader does not perform this check for address cycles rather fixes it as 3-byte address. Hence, there will be no issue when using second-stage boot-loader.

So, when using FX3 ROM boot-loader, it is essential that the MISO line stays LOW until the address cycle is identified. This can be ensured using a pull-down resistor on the MISO line.

Best regards,
Srinath S

View solution in original post

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11 Replies
SrinathS_16
Moderator
Moderator

Hello,

Can you please probe the SPI lines during the CX3 boot and check if there is any activity? If possible, share the captures.

Best regards,

Srinath S

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ArGa_2874246
New Contributor

HI SrinathS_16​,

I could able to see some activities on the SPI lines.

But it was different in the Working and Not Working case.

Not Working Case :

On probing the MISO line, i could see that, some data is read and after that there was no activity.

pastedImage_0.png

Working Case :

On probing the MISO line, i could see that, entire Firmware is read from SPI.

pastedImage_1.png

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SrinathS_16
Moderator
Moderator

Hello,

- In the non-working case, can you please let me know the level of the WP pin?

- Please capture the digital traces on the SPI lines using a logic analyzer and share the same.

- Also, let me know how do you set the BPL bit to '1' manually in your setup.

Best regards,

Srinath S

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ArGa_2874246
New Contributor

Hi SrinathS_16

Please find my reply below.,

- In the non-working case, can you please let me know the level of the WP pin?

     The Level of WP pin is low in non-working case

- Please capture the digital traces on the SPI lines using a logic analyzer and share the same.

     Sorry, Logic analyzer is not available. Below image shows the MISO, MOSI, Clock and Chip Select  in non-working case.

pastedImage_1.png

     From the Graph, before it fails, it reads the data 0x43(C), 0x59(Y), 0x1C, 0xB0.

- Also, let me know how do you set the BPL bit to '1' manually in your setup.

   

     The following sequence is followed to change the status register value to 0x82.,

pastedImage_4.png

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SrinathS_16
Moderator
Moderator

Hello,

- With the SPI Flash present on the FX3 DVK (CYUSB3KIT-001), I modified the SRWD bit (BPL bit equivalent) to 1 and the WP# pin held LOW, I don't find any issues on reading the firmware from the SPI flash.

- The boot-loader does not involve any write command during boot-load.

- Does the second-stage boot-loader work fine when the ROM boot-loader fails?

- Can you please try using a different flash device or on a different board setup and check if there is an issue?

Best regards,

Srinath S

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ArGa_2874246
New Contributor

Hi SrinathS_16​,

I shall check and come up with an answer to your questions. In the meantime, I am confused whether the Tristate in MISO causes boot failure.

In Non-Working case, the MISO line is in Tristate as shown in the below picture,

pastedImage_0.png

Questions :

1. Whether the CX3 samples the Tristate in MISO as logic '1'?

Note:

Tristate level - 1.5 Volts

Logical High - 3.3 Volts 

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ArGa_2874246
New Contributor

Hi SrinathS_16,

Please find my reply below.,

- Does the second-stage boot-loader work fine when the ROM boot-loader fails?

     Yes, the second-stage boot-loader works fine.

- Can you please try using a different flash device or on a different board setup and check if there is an issue?

     We have tried with different board and also with different SPI flash. The same issue occurs.

     Test SPI Flash list:

          1. SST25PF040C-40V/SN

          2. MX25R4035FM1IH1

          3. M25P40-VMN6TPB

Regards,

Arun Muthuganesh

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ArGa_2874246
New Contributor

Hi SrinathS_16

On debugging, we could corner out the case explained below.,

We could see that the Tristate in MISO line is the reason for the issue.

I could relate our issue with the issue discussed in the forum FX3 SPI Boot

Our Findings :

By adding pull down in the MISO line, CX3 is able to boot from SPI flash. As Tristate in MISO line is a valid case, CX3 must be able to boot from SPI without adding pull-down resistor in MISO line.

Questions :

1. Why the Bootloader Firmware alone cannot able to boot from SPI ?

2. Is Tristate in MISO line is a invalid case for CX3 ? Does CX3 samples it as Logic High ?

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SrinathS_16
Moderator
Moderator

Hello Arun Muthuganesh,

- MISO/MOSI lines of FX3 should not have any pull-up or pull-down resistors. When you mention that the MISO line is tri-stated, do you mean to say that the MISO line is left floating? Can you please check if there isn't any pull-up resistor on the line?

- FX3 uses floating state of MISO line during the boot process (Refer FX3™ SPI Boot - KBA88906)

- When the BPL bit of the SPI flash is set to '0', do you not see the tri-state level on the MISO pin?

Best regards,

Srinath S

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ArGa_2874246
New Contributor

Hi SrinathS_16

Please find my in-line reply below.,

- MISO/MOSI lines of FX3 should not have any pull-up or pull-down resistors. When you mention that the MISO line is tri-stated, do you mean to say that the MISO line is left floating? Can you please check if there isn't any pull-up resistor on the line?

  • No, there is no pull-up or pull-down resistor present on MISO Line and On mentioning 'tristate', I mean that the MISO line is left floating.
  • For debugging, we added a pull-down resistor on the MISO line and CX3 is able to boot from SPI Flash.

- FX3 uses floating state of MISO line during the boot process (Refer FX3™ SPI Boot - KBA88906)

  • But on adding pull-down, CX3 is able to boot from SPI flash.  Any comments regarding this?

- When the BPL bit of the SPI flash is set to '0', do you not see the tri-state level on the MISO pin?

  • When BPL bit is set to '0', we are not able to see the tri-state on MISO line.

We have also debugged the behaviour using different SPI flash on Denebola Rev A Board. Please find the details below.,

pastedImage_7.png

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SrinathS_16
Moderator
Moderator

Hello,

- FX3 boot-loader samples the SPI lines during boot-up to identify the number of address bytes. If it samples the MISO line to be logic HIGH (or) floating, it stops sampling the line further for address cycles. Hence, it is essential that the MISO line stays LOW until the FX3 boot-loader identifies the address cycles.

- FX3 second stage boot-loader does not perform this check for address cycles rather fixes it as 3-byte address. Hence, there will be no issue when using second-stage boot-loader.

So, when using FX3 ROM boot-loader, it is essential that the MISO line stays LOW until the address cycle is identified. This can be ensured using a pull-down resistor on the MISO line.

Best regards,
Srinath S

View solution in original post

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