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I have a simple code to read data from FPGA using GPIF II and send via USB. I need only one RD signal to read data from FPGA bus. RD LOW level drive 16 bits data bus. RD HIGH close FPGA data bus and incremet internal FPGA adress counter. Each time I want to read data with different length.
DMA CONFIG code
/*------DMA P-Port config (AUTO mode)---------------------------------------------------------------------------------------------*/
dmaCfg.notification = 0;
dmaCfg.cb = NULL;
dmaCfg.prodSckId = CY_FX_PRODUCER_USB_SOCKET_4;
dmaCfg.consSckId = CY_FX_CONSUMER_PPORT_SOCKET;
dmaCfg.count = 1;
apiRetStatus = CyU3PDmaChannelCreate (&glChHandleSRamUtoP_48, CY_U3P_DMA_TYPE_AUTO, &dmaCfg);
if (apiRetStatus != CY_U3P_SUCCESS)
{
CyU3PDebugPrint (CY_FX_DEBUG_PRIORITY, "CyU3PDmaChannelCreate failed, Error code = %d\n", apiRetStatus);
CyFxAppErrorHandler(apiRetStatus);
}
dmaCfg.notification = 0;
dmaCfg.cb = NULL;
dmaCfg.prodSckId = CY_FX_PRODUCER_PPORT_SOCKET;
dmaCfg.consSckId = CY_FX_CONSUMER_USB_SOCKET_8;
dmaCfg.count = 1;
apiRetStatus = CyU3PDmaChannelCreate (&glChHandleSRamPtoU_48, CY_U3P_DMA_TYPE_AUTO, &dmaCfg);
if (apiRetStatus != CY_U3P_SUCCESS)
{
CyU3PDebugPrint (CY_FX_DEBUG_PRIORITY, "CyU3PDmaChannelconfig Failed, Error code = %d\n", apiRetStatus);
CyFxAppErrorHandler(apiRetStatus);
}
//------------------------------------------------------------------------------------------------------------------------------------------------------------------
Working cycle
for (;;)
{
uint32_t counter = 8;
GpifReadEnd = CyFalse;
CyU3PGpifInitAddrCounter (0, counter, CyFalse, CyTrue, 1); // loading addr count
apiRetStatus = CyU3PGpifSMSwitch (256, RD_START, 256, 0, 0); // start condition after switch GPIF II
if(apiRetStatus != CY_U3P_SUCCESS){
CyU3PDebugPrint (CY_FX_DEBUG_PRIORITY, "CyU3PGpifSMSwitch failed, Error code = %d\r\n", apiRetStatus); }
while(!GpifReadEnd){} // FLAG that assert in interrupt function
GpifReadEnd = CyFalse;
}
Why RD level is LOW after last read cycle on oscilloscope but in GPIF Desinger show RD = HIGH?
When I tried to paste empty state between RD_START state and RD_LOW state, RD signal asserted HIGH, but I have one more read strobe. Why?????????
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Hi,
1) Please check if the signal polarity is set as active high and you de-assert the signal in read_low and assert the signal in read_high
or
2) Please check if the signal polarity is set as active low and you assert the signal in read_low and de-assert the signal in read_high
Please attach your whole state machine project (cydsn folder) for further review.
Regards,
-Madhu Sudhan
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