I'm trying to set different frequency on PIB block. I found that not all dividers are workable when the source is CY_U3P_SYS_CLK. Here are some values that can work.
Others, for example, 48, 64, 100, 128, can't work.
Thanks for reply. When I use the dividers that I mentioned, the host can't recognize the DVK, no device found in control center, neither output on PCLK pin (I checked on scope).