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USB Superspeed Peripherals

poas_4520791
New Contributor II

Hi,

I'm Transfering data from FX3 to FPGA via GPIF II interface.I'm able to transfer only 12 bytes of data through control center and only 9th byte is showing in waveform

The data i'm getting on FPGA side is repeating as shown in below  image.op1.PNG

Regards,

Aswini

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1 Solution
Rashi_Vatsa
Moderator
Moderator

Hello Aswini,

Please program the FX3 with the attached firmware and try to send 512 bytes from the Control center (for USB 2.0) or 1024 bytes for (USB 3.0) and let me know the results.

I have checked it with USB 2.0 at my end and the results are attached.

PCLK - 99MHZ (0.010 us)

SLRD asserted for - 2.56 us - each clock edge 2 bytes data is transferred (as the GPIF interface is 2 bytes) - 512 bytes written from usb > FPGA

Similarly, results are attached for for transferring 32, 128, 256 bytes from USB to FPGA (USB 2.0)

Please check the firmware at your end and let me know the results

Regards,

Rashi

Regards,
Rashi

View solution in original post

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18 Replies
Rashi_Vatsa
Moderator
Moderator

Hello Aswini,

Please confirm that you are using the firmware with the application note AN65974.

Please try the default firmware (with AN 65974) to check the connections of FPGA and FX3

Regards,

Rashi

Regards,
Rashi
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poas_4520791
New Contributor II

Hello,

Yeah i'm using the firmware that is in AN65974 application note.

Regards,

Aswini

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Rashi_Vatsa
Moderator
Moderator

Hello Aswini,

If this is the default firmware, flag c will be 1- not empty 0-empty. From the traces that you have shared, the data is not being consumed on the GPIF side by the FPGA (as flag c is high always)

Please refer to the section 5.1 (read sequence) of the application note AN65974 and let me know if there are any queries

Regards,

Rashi

Regards,
Rashi
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poas_4520791
New Contributor II

Hello,

I'm using the default firmware only,but in GPIF II interface i changed the flags as active high signals whereas in AN65974 application note the signals are active low,with this changes i'm getting 9th byte  of data out of 12 bytes.

Now i'm using the firmware without any changes in GPIF II Interface(flags-active low),then before programming the waveform as shown

below.

before.PNG

After programming the waveform is a below,

after.PNG

Regards,

Aswini

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Rashi_Vatsa
Moderator
Moderator

Hello Aswini,

In the trace (programmed with default firmware), I don't find any assertions on SLRD from the FPGA.

The FPGA needs to control the SLRD/SLWR  to read/write the data from/to FX3

Please go through the timing sequence mentioned in section 5.1 of AN65974 app note for better understanding

Regards,

Rashi

Regards,
Rashi
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poas_4520791
New Contributor II

Hello,

With the Default Firmware i'm getting the result as shown in above two snapshots.But i have made some changes in GPIF II like(I made flags as active high and in transition equation i added DMA_RDY_TH3),with this i'm able to get one byte of data from FX3 to FPGA. After all these changes the signals also asserting properly from FPGA side.

My question is why the remaining bytes are missing,what may be the reason for this?

Regards,

Aswini

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Rashi_Vatsa
Moderator
Moderator

Hello Aswini,

Please share the zoomed traces which shows the assertion of SLRD pin (reading started) with default firmware without any changes

Is the FPGA programmed with bit file provided with the FPGA? or have you programmed the fpga with your custom bit file?

Regards,

Rashi

Regards,
Rashi
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poas_4520791
New Contributor II

Hello,

With default firmware,after programming fx3 is not detecting in the control center .so i changed  GPIF_16_32BIT_CONF  as 0 in slfifisync.h file i.e.,

#define CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT (0).

now it's fine.

Before programming the waveform is as below,default before.PNG

and after programming it is shown as below,

default after.PNG

Here i'm using the  same bit file i'e., provided in AN65974.

Regards,

Aswini

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Rashi_Vatsa
Moderator
Moderator

Hello Aswini,

To debug this problem, please use the default firmware as it is (don't change the initial value  of the pins). if you change the pins polarity without changing the FPGA code the application won't work. If you are using the default bit file which is with the application note you can't change the pins to active high.

Please follow all the steps mentioned in section 11.5.1 of the application note and try reproducing the same as it is.

Please confirm, that you are using Xilinx Spartan 6 FPGA as the bit file in the folder is for SPARTAN 6 FPGA

Regards,

Rashi

Regards,
Rashi
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poas_4520791
New Contributor II

Hello,

Sorry for not being clear .Actually i'm new to this FPGA side .Here i'm using Zynq FPGA with slaveFIFO2b and generated bit file.With the default firmware and generated bit file i'm getting the above waveforms.

Kindly let me know the solution for this.

Regards,

Aswini

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Rashi_Vatsa
Moderator
Moderator

Hello Aswini,

You would need a bit file which is generated for your FPGA. You can't use the bit file which is with the application note.

The application note explains the state machine on the master side (FPGA). You can write a verilog/VHDL code for the your FPGA and generate bit file (after PAR (placement and routing).

OR you can use the FPGA source files in the folder Path: ..\AN65974\FPGA Source files\fx3_slaveFIFO2b_xilinx\rtl_verilog\slaveFIFO2b and map to your FPGA and generate the bit file.

If you want to use the same bit file which is with Application note you have to use Spartan 6 FPGA or Altera Cyclone 3 FPGA

Please let me know if you have any queries on FX3 side.

Regards,

Rashi

Regards,
Rashi
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poas_4520791
New Contributor II

Hello,

Already we have a project of data transmission from  FPGA  to FX3,it's working fine.Now to transmit data from FX3 to FPGA i was strucked here.so,can you help me to resolve this issue.

Regards,

Aswini

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Rashi_Vatsa
Moderator
Moderator

Hello Aswini,

As mentioned in previous response, the SLRD pin is not asserted by the FPGA. If the FX3 state machine doesn't is not able to sample this pin low, the data wouldn't be driven on GPIF lines

Please share the results after trying steps mentioned in section 11.5.1 of the application note.

Regards,

Rashi

Regards,
Rashi
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poas_4520791
New Contributor II

Hello,

Here SLRD signal is asserting by FPGA and the data is also driven by FPGA but only one byte(if i transmit 12 bytes i'm getting 9th byte,11th byte of 16 bytes transmission ,27th byte of 32bytes).

The output for 12 bytes transmission as shown in below images,

1.PNG

2.PNG

What may be the reason for this?

Regards,

Aswini

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Rashi_Vatsa
Moderator
Moderator

Hello Aswini,

Please share the results after following all the steps mentioned in section 11.5.1 of the application note.

Regards,

Rashi

Regards,
Rashi
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Rashi_Vatsa
Moderator
Moderator

Hello Aswini,

Please program the FX3 with the attached firmware and try to send 512 bytes from the Control center (for USB 2.0) or 1024 bytes for (USB 3.0) and let me know the results.

I have checked it with USB 2.0 at my end and the results are attached.

PCLK - 99MHZ (0.010 us)

SLRD asserted for - 2.56 us - each clock edge 2 bytes data is transferred (as the GPIF interface is 2 bytes) - 512 bytes written from usb > FPGA

Similarly, results are attached for for transferring 32, 128, 256 bytes from USB to FPGA (USB 2.0)

Please check the firmware at your end and let me know the results

Regards,

Rashi

Regards,
Rashi

View solution in original post

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poas_4520791
New Contributor II

Hello,

I programmed FX3 with above firmware and the results are as below.

2.PNG

Regards,

Aswini.

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Rashi_Vatsa
Moderator
Moderator

Hello Aswini,

As per the GPIF II state machine, the Data can be read by the FPGA

SLWR : High

SLRD : Low;

SLCS: Low

SLOE : Low

PKTEND: High

Regards,

Rashi

Regards,
Rashi
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