I am new to the FX3 and I wish to use the GPIF II in Synchronous Slave FIFO Interface 32-Bit Data / 2-bit Address. I used FPGA to communication with PC by CYUSB3014,and i used the ControlCenter that Cypress provides ,and programed the img Loop-back to CYUSB3014. When i writing data to FPGA and click the Key "Transfer Data",FPGA could reseive data at once,then i click the Key "Bulk-in",Normally it should show the last written data,It is strange to press three times to display correctly.Fist time all data is zero,the second is zero too,The third time is the right data. It is important that when I clicking the key fist time,I can use signaltap to see the data has been output from the FPGA port. So my question is why must to press three times to display the data correctly, is the internal cache problem?
Attached is my waveform screenshot,Can be seen from the figure that there is almost no delay between the write signal and the data,In addition when I put the data on the port, and then send a write signal, so that the write signal lags behind the data, in the ControlCenter also want to "Bulk-in" three times.