cancel
Showing results for 
Search instead for 
Did you mean: 

USB Superspeed Peripherals

Anonymous
Not applicable

Hi:

   

I am new to the FX3 and I wish to use the GPIF II in Synchronous Slave FIFO Interface 32-Bit Data / 2-bit Address.
I used FPGA to communication with PC by CYUSB3014,and i used the ControlCenter that Cypress provides ,and programed the img Loop-back to CYUSB3014.
When i writing data to FPGA and click the Key "Transfer Data",FPGA could reseive data at once,then i click the Key "Bulk-in",Normally it should show the last written data,It is strange to press three times to display correctly.Fist time all data is zero,the second is zero too,The third time is the right data.
It is important that when I clicking the key fist time,I can use signaltap to see the data has been output from the FPGA port.
So my question is why must to press three times to display the data correctly, is the internal cache problem?   

   

Thanks for help.

0 Likes
2 Replies
Anonymous
Not applicable

Hi,

   

There could be a timing issue between your FPGA Signals. As soon as the SLWR is asserted (made low) by the FPGA, the FPGA should start sending the data.

   

If there is any delay between assertion of SLWR and the point at which the FPGA starts sending data, FX3 starts sampling the data bus without any data and samples all zeros.

   

Please check this,

   

Regards,

   

-Madhu Sudhan

0 Likes
Anonymous
Not applicable

Dear Madhu Sudhan,

   

Attached is my waveform screenshot,Can be seen from the figure that there is almost no delay between the write signal and the data,In addition when I put the data on the port, and then send a write signal, so that the write signal lags behind the data, in the ControlCenter also want to "Bulk-in" three times.

   

Regards,
-Jason Yi

   

   

0 Likes