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USB Superspeed Peripherals

JEv_295166
New Contributor II

The KB article here http://www.cypress.com/knowledge-base-article/gpio-configuration-fx3#comment-418171 states that gpioComplexEn[0] and gpioComplexEn[1] must have a bitmask applied in order to be able to set up specific pins in complex mode.

   

However it fails to say how the bitmask bits map onto the various GPIO pins. 

   

For example I have a GPIF2 design using 8 bit transfers. I'd like to use CTL[0] (GPIO17) as a clock. As far as I can tell, this would mean applying a bitmask of 0x20000 to gpioComplexEn[0]. However this seems to cause the FX3 to fail right from the get-go.

   

Does anyone have a working example and (ideally) a better explanation of these masks? Even the API documentation is extremely light on detail.

   

TAIA

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4 Replies
Anonymous
Not applicable

Yes you are correct. If you have to configure GPIO 17 as simple, you need to set gpioComplexEn[0]/gpioSimpleEn[0] to 0x00020000.

   

By default the GPIF is supposed to be configured as a 16 bit interface where GPIO 17 is set as a control pin by default. Please check you are not using this pin in the GPIF state machine, and the do the following. Do not define this in the IO matrix (don't define 0x00020000), instead, once the CyU3PDeviceConfigureIOMatrix is done without GPIO17, later you need to call CyU3PDeviceGpioOverride to configure the GPIO as a simple/complex and then you can use it as any other GPIO through the firmware.

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JEv_295166
New Contributor II

Hi Nishant and thank you.

   

So far I have been unable to persuade any of the pins in the VIO1 power domain to act as complex GPIO (I am trying to set up one as a clock, it works perfectly for GPIO57 in VIO2). We are using the GPIF (in 8 bit mode) mode but trying to configure GPIO17 always fails. 

   

Also, for the record, if I set the gpioComplexEn[0] member of the io config struct to anything but zero the FX3 SSE board fails immediately at boot time. This is not the case with gpioComplexEn[1]! Any thoughts?

   

TAIA.

   

Here's a snippet that works with 50 but not 17

   
    status = CyU3PDeviceGpioOverride(X_CLOCK_GPIO, CyTrue);     if (status != 0)     {         dbg_printf("GPIO Override failed, Error Code = %d",status);         CyFxAppErrorHandler(status);     }      // Configure GPIO 50 as PWM output     // 50 is SSE I2S_CLCK     gpioConfig.outValue = CyFalse;     gpioConfig.inputEn = CyFalse;     gpioConfig.driveLowEn = CyTrue;     gpioConfig.driveHighEn = CyTrue;     gpioConfig.pinMode = CY_U3P_GPIO_MODE_PWM;     gpioConfig.pinMode = CY_U3P_GPIO_MODE_TOGGLE;     gpioConfig.intrMode = CY_U3P_GPIO_NO_INTR;     gpioConfig.timerMode = CY_U3P_GPIO_TIMER_HIGH_FREQ;     gpioConfig.timer = 0;     gpioConfig.period = 5;     gpioConfig.threshold = 2;     status = CyU3PGpioSetComplexConfig(X_CLOCK_GPIO, &gpioConfig);     if (status != CY_U3P_SUCCESS)     {         dbg_printf("Failure: error code = %d Pin: 0x%x (%d)", status, X_CLOCK_GPIO, X_CLOCK_GPIO);         CyFxAppErrorHandler(status);     }
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Anonymous
Not applicable


Simple GPIO: status = CyU3PDeviceGpioOverride(X_CLOCK_GPIO, CyTrue);

   

for complex, you need to change the 2nd argument:
status = CyU3PDeviceGpioOverride(X_CLOCK_GPIO, CyFalse);

   

 

   

Also, note: There are eight complex I/O pin groups, the elements of which are chosen in a modulo 8 fashion (complex I/O group 0: GPIO 0, 8, 16; complex I/O group 1: GPIO 1, 9, 17, and so on). Only one pin from a group can use the complex I/O functions.
 

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JEv_295166
New Contributor II

Hello Nishant

   

Thanks again for your help. I had completely overlooked the 2nd parameter to CyU3PDeviceGpioOverride(). One thing to note however, the complex mode set up of the pin in question (GPIO 50, I2S_CLK on the SSE) _does_ work with the 'isSimple' argument set to CyTrue. 

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